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author | Tristan Gingold <tgingold@free.fr> | 2019-05-11 07:15:10 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-11 18:13:37 +0200 |
commit | 8c03cadc09ad28f0dba75b85e0e6f48667c4e6d6 (patch) | |
tree | 9d820a10cccd80f00dc35e7da391117ebf0ef245 /testsuite/gna/issue817/repro1.vhdl | |
parent | 58b3b8a09770e36e36d2d6f870dac2df00457b14 (diff) | |
download | ghdl-8c03cadc09ad28f0dba75b85e0e6f48667c4e6d6.tar.gz ghdl-8c03cadc09ad28f0dba75b85e0e6f48667c4e6d6.tar.bz2 ghdl-8c03cadc09ad28f0dba75b85e0e6f48667c4e6d6.zip |
Add testcase for #817
Diffstat (limited to 'testsuite/gna/issue817/repro1.vhdl')
-rw-r--r-- | testsuite/gna/issue817/repro1.vhdl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/gna/issue817/repro1.vhdl b/testsuite/gna/issue817/repro1.vhdl new file mode 100644 index 000000000..4ff7d8bd9 --- /dev/null +++ b/testsuite/gna/issue817/repro1.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end entity; + +architecture arch of ent is +begin + process + variable valid_tmp : std_logic_vector := (others => '0'); + begin + valid_tmp := (others => '0'); + wait; + end process; +end architecture; |