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author | Tristan Gingold <tgingold@free.fr> | 2019-03-12 19:07:21 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-03-14 07:14:44 +0100 |
commit | bdf042b5b55d695f5a312bb09699503c5519858f (patch) | |
tree | 64d236806dac7726b7815e73c888719de23c2a1c /testsuite/gna/issue776 | |
parent | 145aa829f2b9166039442638e078f8aac5940ac6 (diff) | |
download | ghdl-bdf042b5b55d695f5a312bb09699503c5519858f.tar.gz ghdl-bdf042b5b55d695f5a312bb09699503c5519858f.tar.bz2 ghdl-bdf042b5b55d695f5a312bb09699503c5519858f.zip |
Add testcase for #776
Diffstat (limited to 'testsuite/gna/issue776')
-rw-r--r-- | testsuite/gna/issue776/main.vhdl | 50 | ||||
-rw-r--r-- | testsuite/gna/issue776/my_top.vhdl | 9 | ||||
-rwxr-xr-x | testsuite/gna/issue776/testsuite.sh | 19 |
3 files changed, 78 insertions, 0 deletions
diff --git a/testsuite/gna/issue776/main.vhdl b/testsuite/gna/issue776/main.vhdl new file mode 100644 index 000000000..f736ab4f4 --- /dev/null +++ b/testsuite/gna/issue776/main.vhdl @@ -0,0 +1,50 @@ +library ieee; +use ieee.std_logic_1164.all; +entity HA_Entity is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); +end HA_Entity; +architecture HA_Arch of HA_Entity is + component HA_Comp is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); + end component HA_Comp; +begin + HA_Inst : HA_Comp + port map ( + i_bit1 => i_bit1, + i_bit2 => i_bit2, + o_sum => o_sum, + o_carry => o_carry); +end HA_Arch; +library ieee; +use ieee.std_logic_1164.all; +entity HA_Comp_Entity is + port ( + i_bit1 : in std_logic; + i_bit2 : in std_logic; + o_sum : out std_logic; + o_carry : out std_logic + ); +end HA_Comp_Entity; +architecture HA_Comp_Arch_1 of HA_Comp_Entity is +begin + o_sum <= i_bit1 xor i_bit2; + o_carry <= i_bit1 and i_bit2; +end HA_Comp_Arch_1; +use work.all; +configuration HA_Config of HA_Entity is + for HA_Arch + for HA_Inst : HA_Comp + use entity HA_Comp_Entity(HA_Comp_Arch_1); + end for; + end for; +end HA_Config; diff --git a/testsuite/gna/issue776/my_top.vhdl b/testsuite/gna/issue776/my_top.vhdl new file mode 100644 index 000000000..c2e5eb1cb --- /dev/null +++ b/testsuite/gna/issue776/my_top.vhdl @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity my_top is end entity; + +architecture my_top_impl of my_top is +begin + HA_Entity_instance: entity work.HA_Entity port map('0', '0'); +end architecture; diff --git a/testsuite/gna/issue776/testsuite.sh b/testsuite/gna/issue776/testsuite.sh new file mode 100755 index 000000000..72fbe3ae2 --- /dev/null +++ b/testsuite/gna/issue776/testsuite.sh @@ -0,0 +1,19 @@ +#! /bin/sh + +. ../../testenv.sh + +#export GHDL_STD_FLAGS=--std=08 +analyze main.vhdl +elab_simulate HA_Entity +elab_simulate HA_Config +analyze my_top.vhdl +elab_simulate ha_config +if elab_simulate ha_config my_top; then + echo "failure expected" + exit 1; +fi + + +clean + +echo "Test successful" |