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author | Tristan Gingold <tgingold@free.fr> | 2021-09-07 21:19:42 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-07 21:19:42 +0200 |
commit | 930bfe7d5aefbb88e80a92991a372c9e822558b0 (patch) | |
tree | 4c8596beb5bbe866e95d4c119d4035104a49c3ab /testsuite/gna/issue737/ent1.vhdl | |
parent | 4341334801df81f31bcca25ab4840be2f8c95c22 (diff) | |
download | ghdl-930bfe7d5aefbb88e80a92991a372c9e822558b0.tar.gz ghdl-930bfe7d5aefbb88e80a92991a372c9e822558b0.tar.bz2 ghdl-930bfe7d5aefbb88e80a92991a372c9e822558b0.zip |
testsuite/gna: add a test for #737
Diffstat (limited to 'testsuite/gna/issue737/ent1.vhdl')
-rw-r--r-- | testsuite/gna/issue737/ent1.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/gna/issue737/ent1.vhdl b/testsuite/gna/issue737/ent1.vhdl new file mode 100644 index 000000000..71a98b1b6 --- /dev/null +++ b/testsuite/gna/issue737/ent1.vhdl @@ -0,0 +1,12 @@ +entity ent1 is +end entity; + +architecture impl of ent1 is + type bitvv is array(natural range <>) of bit_vector; + signal foo: bitvv(2 downto 0)(0 downto 0); + signal foo1 : bitvv(1 downto 0)(0 downto 0); +begin + +foo1 <= foo(1 downto 0); + +end architecture; |