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authorTristan Gingold <tgingold@free.fr>2021-09-07 21:19:42 +0200
committerTristan Gingold <tgingold@free.fr>2021-09-07 21:19:42 +0200
commit930bfe7d5aefbb88e80a92991a372c9e822558b0 (patch)
tree4c8596beb5bbe866e95d4c119d4035104a49c3ab /testsuite/gna/issue737/ent1.vhdl
parent4341334801df81f31bcca25ab4840be2f8c95c22 (diff)
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testsuite/gna: add a test for #737
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diff --git a/testsuite/gna/issue737/ent1.vhdl b/testsuite/gna/issue737/ent1.vhdl
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+entity ent1 is
+end entity;
+
+architecture impl of ent1 is
+ type bitvv is array(natural range <>) of bit_vector;
+ signal foo: bitvv(2 downto 0)(0 downto 0);
+ signal foo1 : bitvv(1 downto 0)(0 downto 0);
+begin
+
+foo1 <= foo(1 downto 0);
+
+end architecture;