Add testcase #652

2 files changed, 44 insertions, 0 deletions

diff --git a/testsuite/gna/issue652/ent.vhdl b/testsuite/gna/issue652/ent.vhdl
new file mode 100644
index 000000000..00757ae13
--- /dev/null
+++ b/testsuite/gna/issue652/ent.vhdl
@@ -0,0 +1,35 @@
+entity clock_Generator is
+	port (
+		Clock : out bit
+	);
+end entity;
+
+entity clock_Monitor is
+	port (
+		Clock : in bit
+	);
+end entity;
+
+package clock is
+end package;
+
+
+library Clock;
+use     Clock.clock.all;
+
+entity test is
+end entity;
+
+architecture tb of test is
+  signal Clock        : bit;
+begin
+	gen: entity Clock.clock_Generator
+		port map (
+			Clock       => Clock
+		);
+	
+	mon: entity Clock.clock_Monitor
+		port map (
+			Clock       => Clock
+		);
+end architecture;
diff --git a/testsuite/gna/issue652/testsuite.sh b/testsuite/gna/issue652/testsuite.sh
new file mode 100755
index 000000000..4ffa83126
--- /dev/null
+++ b/testsuite/gna/issue652/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure --work=clock ent.vhdl
+
+clean
+
+echo "Test successful"