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author | Tristan Gingold <tgingold@free.fr> | 2018-11-22 20:47:08 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-22 20:47:08 +0100 |
commit | 3d81a74f66c2440ebde7efc64415d6c5510e94ee (patch) | |
tree | 3e3587bb54d970ac1fcd25a0e83cb9909a70e985 /testsuite/gna/issue473/tbmem.vhdl | |
parent | 69c5ab150001ae0866aaaca6cbcdf38e0264a296 (diff) | |
download | ghdl-3d81a74f66c2440ebde7efc64415d6c5510e94ee.tar.gz ghdl-3d81a74f66c2440ebde7efc64415d6c5510e94ee.tar.bz2 ghdl-3d81a74f66c2440ebde7efc64415d6c5510e94ee.zip |
Add testcase for #473
Diffstat (limited to 'testsuite/gna/issue473/tbmem.vhdl')
-rw-r--r-- | testsuite/gna/issue473/tbmem.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/gna/issue473/tbmem.vhdl b/testsuite/gna/issue473/tbmem.vhdl new file mode 100644 index 000000000..a31a29520 --- /dev/null +++ b/testsuite/gna/issue473/tbmem.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tbmem is +end entity tbmem; + +architecture TB of tbmem is + +begin + + DM: process + type t_ram is array(natural range <>) of unsigned; + type p_ram is access t_ram; + variable myram : p_ram; + begin + myram := new t_ram(0 to 31)(15 downto 0); + for i in myram'range loop + myram(i) := TO_UNSIGNED(i, 16); + end loop; + for i in myram'range loop + report integer'image(i) & ": " & TO_HSTRING(myram(i)); + end loop; + wait; + end process DM; + +end architecture TB; |