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authorTristan Gingold <tgingold@free.fr>2018-11-22 20:47:08 +0100
committerTristan Gingold <tgingold@free.fr>2018-11-22 20:47:08 +0100
commit3d81a74f66c2440ebde7efc64415d6c5510e94ee (patch)
tree3e3587bb54d970ac1fcd25a0e83cb9909a70e985 /testsuite/gna/issue473/tbmem.vhdl
parent69c5ab150001ae0866aaaca6cbcdf38e0264a296 (diff)
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Add testcase for #473
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diff --git a/testsuite/gna/issue473/tbmem.vhdl b/testsuite/gna/issue473/tbmem.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tbmem is
+end entity tbmem;
+
+architecture TB of tbmem is
+
+begin
+
+ DM: process
+ type t_ram is array(natural range <>) of unsigned;
+ type p_ram is access t_ram;
+ variable myram : p_ram;
+ begin
+ myram := new t_ram(0 to 31)(15 downto 0);
+ for i in myram'range loop
+ myram(i) := TO_UNSIGNED(i, 16);
+ end loop;
+ for i in myram'range loop
+ report integer'image(i) & ": " & TO_HSTRING(myram(i));
+ end loop;
+ wait;
+ end process DM;
+
+end architecture TB;