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author | Tristan Gingold <tgingold@free.fr> | 2017-11-29 06:20:48 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-11-29 06:20:48 +0100 |
commit | 9a2c3a862738d8e168b8180f616e733038fdfb61 (patch) | |
tree | f6efa8c20485049489224205453b38939279f809 /testsuite/gna/issue472 | |
parent | 99605e5b867572c25ad375b79c8c822ea82a18ed (diff) | |
download | ghdl-9a2c3a862738d8e168b8180f616e733038fdfb61.tar.gz ghdl-9a2c3a862738d8e168b8180f616e733038fdfb61.tar.bz2 ghdl-9a2c3a862738d8e168b8180f616e733038fdfb61.zip |
Testcase for #472
Diffstat (limited to 'testsuite/gna/issue472')
-rw-r--r-- | testsuite/gna/issue472/test.vhdl | 14 | ||||
-rwxr-xr-x | testsuite/gna/issue472/testsuite.sh | 9 |
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/gna/issue472/test.vhdl b/testsuite/gna/issue472/test.vhdl new file mode 100644 index 000000000..9f196078b --- /dev/null +++ b/testsuite/gna/issue472/test.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is + port ( + input : boolean + ); +end test; + +architecture behaviour of test is + signal foo : std_logic; +begin + foo <= "0" when input else "1"; -- Note: Should be '0' and '1' instead +end behaviour; diff --git a/testsuite/gna/issue472/testsuite.sh b/testsuite/gna/issue472/testsuite.sh new file mode 100755 index 000000000..8e20eb85f --- /dev/null +++ b/testsuite/gna/issue472/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure test.vhdl + +clean + +echo "Test successful" |