Add issue40 testcase.

3 files changed, 81 insertions, 0 deletions

diff --git a/testsuite/gna/issue40/test.vhdl b/testsuite/gna/issue40/test.vhdl
new file mode 100644
index 000000000..ca00ece42
--- /dev/null
+++ b/testsuite/gna/issue40/test.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity a is
+port
+(
+    foo : in std_ulogic_vector
+);
+end a;
+
+architecture rtl of a is
+begin
+end rtl;
+
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity b is
+port
+(
+    bar     : inout std_logic_vector(7 downto 0)
+);
+end b;
+
+architecture rtl of b is
+begin
+
+i_a: entity work.a
+port map
+(
+    foo => std_ulogic_vector(bar)
+);
+end rtl;
+
diff --git a/testsuite/gna/issue40/test2.vhdl b/testsuite/gna/issue40/test2.vhdl
new file mode 100644
index 000000000..e9d2a5489
--- /dev/null
+++ b/testsuite/gna/issue40/test2.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity a2 is
+port
+(
+    foo : out std_ulogic_vector
+);
+end;
+
+architecture rtl of a2 is
+begin
+end rtl;
+
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity b2 is
+port
+(
+    bar     : inout std_logic_vector(7 downto 0)
+);
+end;
+
+architecture rtl of b2 is
+begin
+
+i_a: entity work.a2
+port map
+(
+    std_logic_vector (foo) => bar
+);
+end rtl;
+
diff --git a/testsuite/gna/issue40/testsuite.sh b/testsuite/gna/issue40/testsuite.sh
new file mode 100755
index 000000000..91c95c926
--- /dev/null
+++ b/testsuite/gna/issue40/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+analyze_failure test.vhdl
+analyze_failure test2.vhdl
+
+clean
+
+echo "Test successful"