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| author | Tristan Gingold <tgingold@free.fr> | 2017-06-27 20:31:28 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-06-27 20:31:28 +0200 |
| commit | 59869f0e517c69632da810c1a42aada26e537e32 (patch) | |
| tree | d801346bda9068551a7f6bd0ddb4596cc9128c94 /testsuite/gna/issue375/cond_assign_proc.vhdl | |
| parent | af582493c5767edf39a21c0f68e2cd6a3d3b3d2b (diff) | |
| download | ghdl-59869f0e517c69632da810c1a42aada26e537e32.tar.gz ghdl-59869f0e517c69632da810c1a42aada26e537e32.tar.bz2 ghdl-59869f0e517c69632da810c1a42aada26e537e32.zip | |
Testcase for #375
Diffstat (limited to 'testsuite/gna/issue375/cond_assign_proc.vhdl')
| -rw-r--r-- | testsuite/gna/issue375/cond_assign_proc.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/issue375/cond_assign_proc.vhdl b/testsuite/gna/issue375/cond_assign_proc.vhdl new file mode 100644 index 000000000..0ae81ed96 --- /dev/null +++ b/testsuite/gna/issue375/cond_assign_proc.vhdl @@ -0,0 +1,26 @@ +library ieee ;
+use ieee.std_logic_1164.all ;
+use std.textio.all ;
+
+entity cond_assign_proc is
+end entity cond_assign_proc;
+
+architecture doit of cond_assign_proc is
+ signal Clk : std_logic := '0' ;
+ signal Y : std_logic ;
+begin
+ Clk <= not Clk after 10 ns ;
+
+ process (all)
+ begin
+ Y <= '1' when Clk = '1' else '0' ;
+ end process ;
+
+ process
+ begin
+ wait for 500 ns ;
+ std.env.stop ;
+ end process ;
+end architecture doit ;
+
+
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