Add testcases for #238

12 files changed, 198 insertions, 0 deletions

diff --git a/testsuite/gna/issue238/assign1.vhdl b/testsuite/gna/issue238/assign1.vhdl
new file mode 100644
index 000000000..4bd68b008
--- /dev/null
+++ b/testsuite/gna/issue238/assign1.vhdl
@@ -0,0 +1,21 @@
+entity assign1 is
+end;
+
+use work.pkg.all;
+
+architecture behav of assign1 is
+begin
+  process
+   variable v : rec_4;
+  begin
+    v.a := 5;
+    assert v.a = 5 severity failure;
+
+    v.s := "Good";
+    assert v.a = 5 severity failure;
+    assert v.s = "Good" severity failure;
+
+    assert false report "ok" severity note;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/cst.vhdl b/testsuite/gna/issue238/cst.vhdl
new file mode 100644
index 000000000..a98663f98
--- /dev/null
+++ b/testsuite/gna/issue238/cst.vhdl
@@ -0,0 +1,10 @@
+package cst is
+  function four return natural;
+end cst;
+
+package body cst is
+  function four return natural is
+  begin
+    return 4;
+  end four;
+end cst;
diff --git a/testsuite/gna/issue238/pkg.vhdl b/testsuite/gna/issue238/pkg.vhdl
new file mode 100644
index 000000000..3b5fb23e4
--- /dev/null
+++ b/testsuite/gna/issue238/pkg.vhdl
@@ -0,0 +1,14 @@
+use work.cst.all;
+
+package pkg is
+  type rec is record
+    s : string;
+    a : integer;
+  end record;
+
+  constant cfour : natural := work.cst.four;
+
+  subtype rec_4 is rec (s(1 to 4));
+  subtype rec_4bis is rec (s(1 to 4));
+  subtype rec_4dyn is rec (s(1 to cfour));
+end pkg;
diff --git a/testsuite/gna/issue238/proc1.vhdl b/testsuite/gna/issue238/proc1.vhdl
new file mode 100644
index 000000000..103e2855a
--- /dev/null
+++ b/testsuite/gna/issue238/proc1.vhdl
@@ -0,0 +1,26 @@
+entity proc1 is
+end;
+
+use work.pkg.all;
+
+architecture behav of proc1 is
+  procedure proc (v : inout rec) is
+  begin
+    v.a := 5;
+    assert v.a = 5 severity failure;
+
+    v.s := "Good";
+    assert v.a = 5 severity failure;
+    assert v.s = "Good" severity failure;
+
+    assert false report "ok" severity note;
+  end proc;
+  
+begin
+  process
+   variable v : rec_4;
+  begin
+    proc (v);
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/rec2.vhdl b/testsuite/gna/issue238/rec2.vhdl
new file mode 100644
index 000000000..7ab1ec9fb
--- /dev/null
+++ b/testsuite/gna/issue238/rec2.vhdl
@@ -0,0 +1,24 @@
+entity rec2 is
+end;
+
+architecture behav of rec2 is
+  type rec1 is record
+    a : natural;
+  end record;
+
+  type rec1_arr is array (natural range <>) of rec1;
+
+  function resolve (a : rec1_arr) return rec1 is
+  begin
+    return (a => 0);
+  end resolve;
+
+  subtype srec1 is resolve rec1;
+begin
+  process
+    variable a : srec1;
+  begin
+    a.a := 5;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/repro1.vhdl b/testsuite/gna/issue238/repro1.vhdl
new file mode 100644
index 000000000..5dcbf8e76
--- /dev/null
+++ b/testsuite/gna/issue238/repro1.vhdl
@@ -0,0 +1,15 @@
+ENTITY repro1 IS
+  TYPE foo_t IS RECORD
+    bar : bit_vector;
+  END RECORD foo_t;
+END ENTITY repro1;
+
+ARCHITECTURE bar OF repro1 IS
+BEGIN
+  process
+    variable baz : foo_t(bar(1 DOWNTO 0));
+  begin
+    wait;
+  end process;
+
+END ARCHITECTURE bar;
diff --git a/testsuite/gna/issue238/test.vhdl b/testsuite/gna/issue238/test.vhdl
new file mode 100644
index 000000000..c25046d3f
--- /dev/null
+++ b/testsuite/gna/issue238/test.vhdl
@@ -0,0 +1,15 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY test IS
+  TYPE foo_t IS RECORD
+    bar : unsigned;
+  END RECORD foo_t;
+END ENTITY test;
+
+ARCHITECTURE bar OF test IS
+  SIGNAL baz : foo_t(bar(1 DOWNTO 0));
+BEGIN
+
+END ARCHITECTURE bar;
diff --git a/testsuite/gna/issue238/testsuite.sh b/testsuite/gna/issue238/testsuite.sh
new file mode 100755
index 000000000..368be0f47
--- /dev/null
+++ b/testsuite/gna/issue238/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+#analyze test.vhdl
+#elab_simulate test
+
+analyze cst.vhdl pkg.vhdl
+analyze var1.vhdl var2.vhdl var3.vhdl var4.vhdl
+analyze assign1.vhdl proc1.vhdl 
+elab_simulate proc1
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue238/var1.vhdl b/testsuite/gna/issue238/var1.vhdl
new file mode 100644
index 000000000..b77557ca8
--- /dev/null
+++ b/testsuite/gna/issue238/var1.vhdl
@@ -0,0 +1,13 @@
+entity var1 is
+end;
+
+use work.pkg.all;
+
+architecture behav of var1 is
+begin
+  process
+   variable v : rec_4;
+  begin
+   wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/var2.vhdl b/testsuite/gna/issue238/var2.vhdl
new file mode 100644
index 000000000..0b488a0cb
--- /dev/null
+++ b/testsuite/gna/issue238/var2.vhdl
@@ -0,0 +1,14 @@
+entity var2 is
+end;
+
+use work.pkg.all;
+
+architecture behav of var2 is
+begin
+  process
+   variable v1, v2 : rec_4;
+  begin
+   v2 := v1;
+   wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/var3.vhdl b/testsuite/gna/issue238/var3.vhdl
new file mode 100644
index 000000000..c34cba102
--- /dev/null
+++ b/testsuite/gna/issue238/var3.vhdl
@@ -0,0 +1,15 @@
+entity var3 is
+end;
+
+use work.pkg.all;
+
+architecture behav of var3 is
+begin
+  process
+   variable v1 : rec_4;
+   variable v2 : rec_4bis;
+  begin
+   v2 := v1;
+   wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue238/var4.vhdl b/testsuite/gna/issue238/var4.vhdl
new file mode 100644
index 000000000..97457a53d
--- /dev/null
+++ b/testsuite/gna/issue238/var4.vhdl
@@ -0,0 +1,15 @@
+entity var4 is
+end;
+
+use work.pkg.all;
+
+architecture behav of var4 is
+begin
+  process
+   variable v1 : rec_4;
+   variable v2 : rec_4dyn;
+  begin
+   v2 := v1;
+   wait;
+  end process;
+end behav;