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author | Thomas Hiscock <thomas.hiscock@wanadoo.fr> | 2017-01-05 21:02:13 +0100 |
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committer | Thomas Hiscock <thomas.hiscock@wanadoo.fr> | 2017-01-05 21:42:07 +0100 |
commit | 46b02a2f1217646ee475e5169a372690d88255ea (patch) | |
tree | af57d47fc380869da9cbdbd05d177ef27e6f8f12 /testsuite/gna/issue228 | |
parent | 603e2fe204cb578e2ac3f67b80a1c447205d40b2 (diff) | |
download | ghdl-46b02a2f1217646ee475e5169a372690d88255ea.tar.gz ghdl-46b02a2f1217646ee475e5169a372690d88255ea.tar.bz2 ghdl-46b02a2f1217646ee475e5169a372690d88255ea.zip |
removing PSL coverage hit default report
It closes #228.
Nothing is displayed unless the user specifies a report statement.
Testcase added to check this behaviour.
Diffstat (limited to 'testsuite/gna/issue228')
-rw-r--r-- | testsuite/gna/issue228/tb.vhdl | 61 | ||||
-rwxr-xr-x | testsuite/gna/issue228/testsuite.sh | 15 |
2 files changed, 76 insertions, 0 deletions
diff --git a/testsuite/gna/issue228/tb.vhdl b/testsuite/gna/issue228/tb.vhdl new file mode 100644 index 000000000..4dfaf3cf3 --- /dev/null +++ b/testsuite/gna/issue228/tb.vhdl @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity foo is + port ( + clk : in std_ulogic; + a0 : in std_ulogic + ); +end entity; + +architecture bar of foo is +begin + -- psl default clock is rising_edge(clk); + -- psl sequence rising_a0 is {not(a0); a0}; + -- psl sequence falling_a0 is {a0; not(a0)}; + -- psl cover {rising_a0}; + -- psl cover {falling_a0} report "falling_a0 custom report"; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity foo_tb is +end entity; + +architecture tb of foo_tb is + signal clk : std_ulogic := '0'; + signal a0 : std_ulogic; +begin + + clk_gen: + process + begin + for i in 0 to 10 loop + clk <= not(clk); + wait for 10 ns; + end loop; + wait; + end process; + + test_driver: + process + begin + a0 <= '1'; + wait until rising_edge(clk); + a0 <= '0'; + wait until rising_edge(clk); + a0 <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait; + end process; + + dut: + entity work.foo(bar) + port map ( + clk => clk, + a0 => a0); + +end architecture; diff --git a/testsuite/gna/issue228/testsuite.sh b/testsuite/gna/issue228/testsuite.sh new file mode 100755 index 000000000..437efa718 --- /dev/null +++ b/testsuite/gna/issue228/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=-fpsl +analyze tb.vhdl +elab_simulate foo_tb 2>sim_log.txt + +run "grep -q 'falling_a0 custom report' sim_log.txt" +run_failure "grep -q 'sequence covered' sim_log.txt" + +rm -f sim_log.txt +clean + +echo "Test successful" |