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author | Tristan Gingold <tgingold@free.fr> | 2022-08-10 16:55:22 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-08-10 16:55:22 +0200 |
commit | 4d14b77ce02b89b1a22718ce607b16d823d95c74 (patch) | |
tree | 6090f74b784e4768a6c1d7f8da9890f6da129f93 /testsuite/gna/issue2166/sram.vhdl | |
parent | 8a3922778cd92df96aaf5771f24d650bb8290559 (diff) | |
download | ghdl-4d14b77ce02b89b1a22718ce607b16d823d95c74.tar.gz ghdl-4d14b77ce02b89b1a22718ce607b16d823d95c74.tar.bz2 ghdl-4d14b77ce02b89b1a22718ce607b16d823d95c74.zip |
testsuite/gna: add a reproducer for #2166
Diffstat (limited to 'testsuite/gna/issue2166/sram.vhdl')
-rw-r--r-- | testsuite/gna/issue2166/sram.vhdl | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/testsuite/gna/issue2166/sram.vhdl b/testsuite/gna/issue2166/sram.vhdl new file mode 100644 index 000000000..ac8b7ae8a --- /dev/null +++ b/testsuite/gna/issue2166/sram.vhdl @@ -0,0 +1,44 @@ +library ieee ; +use ieee.std_logic_1164.all ; +use ieee.numeric_std.all ; +library OSVVM ; +use OSVVM.MemoryPkg.all; + +Entity SRAM is + port ( + Address : in std_logic_vector (19 downto 0) ; + Data : inout std_logic_vector (15 downto 0) ; + nCE :in std_logic; + nOE :in std_logic; + nWE :in std_logic + ); +end SRAM ; + +Architecture model of SRAM is + signal MemoryID : MemoryIDType ; + signal WriteEnable, ReadEnable : std_logic ; +begin + MemoryID <= NewID( + Name => SRAM'instance_name, + AddrWidth => Address'length, + DataWidth => Data'length) ; + WriteEnable <= not nWE and not nCE ; + + RamWriteProc : process + begin + wait until falling_edge(WriteEnable) ; + MemWrite(MemoryID, Address, Data) ; + end process RamWriteProc ; + + ReadEnable <= not nCE and not nOE ; + + ReadProc : process + begin + wait on Address, ReadEnable ; + case ReadEnable is + when '1' => Data <= MemRead(MemoryID, Address) ; + when '0' => Data <= (Data'range => 'Z') ; + when others => Data <= (Data'range => 'X') ; + end case ; + end process ReadProc ; +end model ; |