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authorTristan Gingold <tgingold@free.fr>2022-07-21 21:35:27 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-21 21:35:27 +0200
commit79d140f39eb30e78655ecf448df8be48d22f6af3 (patch)
tree807758453949bb7f8c1d6959afdc06c682b2d21d /testsuite/gna/issue2136/test.vhdl
parent0051b3bca69ff96e8410a5f5fb8d588d4df25ce2 (diff)
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testsuite/gna: add a test for #2136
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diff --git a/testsuite/gna/issue2136/test.vhdl b/testsuite/gna/issue2136/test.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+entity test is
+end;
+
+architecture BHV of test is
+ type matrixType is array(natural range <>) of std_logic_vector;
+
+ function get_min( a : matrixType) return std_logic_vector is
+ variable res : a'element;
+ begin
+ report "a: " & natural'image(a'left) & natural'image (a'right);
+ res:=a(a'left);
+ for i in a'range loop
+ if (a(i)<res) then
+ res:=a(i);
+ end if;
+ end loop;
+ return res;
+ end function get_min;
+
+ signal matrix1 : matrixType(0 to 1)(7 downto 0):=(x"80",x"10");
+ signal min1 : std_logic_vector (7 downto 0);
+
+begin
+
+ min1 <= get_min(matrix1);
+
+end;