diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-07-02 07:40:14 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-02 07:40:14 +0200 |
| commit | 87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869 (patch) | |
| tree | 237dcf1674057fbeb1e1bf7125a72aa5b5669d40 /testsuite/gna/issue2116/aspect03.vhdl | |
| parent | 9b5de7a92a6ae8980bcaad0d1c87f0938c337f21 (diff) | |
| download | ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.tar.gz ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.tar.bz2 ghdl-87ab6659b16c7c7a3a63cb4d3987aa2a02ae5869.zip | |
testsuite/gna: add tests, close #2116
Diffstat (limited to 'testsuite/gna/issue2116/aspect03.vhdl')
| -rw-r--r-- | testsuite/gna/issue2116/aspect03.vhdl | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/testsuite/gna/issue2116/aspect03.vhdl b/testsuite/gna/issue2116/aspect03.vhdl new file mode 100644 index 000000000..4d0875615 --- /dev/null +++ b/testsuite/gna/issue2116/aspect03.vhdl @@ -0,0 +1,6 @@ +library ieee;use ieee.std_logic_1164.all;entity dut is +port(sig_i:std_logic_vector;sig_o:out std_logic_vector);end entity;architecture a of dut is +begin sig_o<=sig_i;end architecture;library ieee;use ieee.std_logic_1164.all;entity tb is +end entity;architecture h of tb is +signal s:std_logic_vector(0 to 0);signal s0:std_logic_vector(0 downto 0);begin process begin +wait for ns;report to_string(0);report to_string(0);end process;t:entity k't port map(0);end architecture;
\ No newline at end of file |