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author | Tristan Gingold <tgingold@free.fr> | 2022-03-05 07:25:17 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-03-05 07:25:17 +0100 |
commit | 311e9448678c6c8ecf1af3dcd7f98c5cd1437c77 (patch) | |
tree | b7322eb14c2aaa2e7e9a06c1fd931dbcfccce80c /testsuite/gna/issue1994/tb.vhdl | |
parent | 74c13245329ca052bd5e529ebb6230562504dfee (diff) | |
download | ghdl-311e9448678c6c8ecf1af3dcd7f98c5cd1437c77.tar.gz ghdl-311e9448678c6c8ecf1af3dcd7f98c5cd1437c77.tar.bz2 ghdl-311e9448678c6c8ecf1af3dcd7f98c5cd1437c77.zip |
testsuite/gna: add a test for #1994
Diffstat (limited to 'testsuite/gna/issue1994/tb.vhdl')
-rw-r--r-- | testsuite/gna/issue1994/tb.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/gna/issue1994/tb.vhdl b/testsuite/gna/issue1994/tb.vhdl new file mode 100644 index 000000000..fa5663903 --- /dev/null +++ b/testsuite/gna/issue1994/tb.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb is +end entity; + +architecture sim of tb is + signal clk : std_logic := '1'; +begin + clk <= not clk after 100 ms; -- period / 2; + process is + begin + wait until rising_edge(clk); + end process; +end architecture; |