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author | Tristan Gingold <tgingold@free.fr> | 2016-09-13 07:52:40 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-09-13 07:52:40 +0200 |
commit | 707123f09bb373ce6d239d406121c220e3ba7813 (patch) | |
tree | efc58271f485b9211c05785098dbf0ee0f5f0a17 /testsuite/gna/issue150/concat2.vhdl | |
parent | b14c63e70136fbb134739ed53cc0f49b14ab5c90 (diff) | |
download | ghdl-707123f09bb373ce6d239d406121c220e3ba7813.tar.gz ghdl-707123f09bb373ce6d239d406121c220e3ba7813.tar.bz2 ghdl-707123f09bb373ce6d239d406121c220e3ba7813.zip |
Add testcase from issue #150
Diffstat (limited to 'testsuite/gna/issue150/concat2.vhdl')
-rw-r--r-- | testsuite/gna/issue150/concat2.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/gna/issue150/concat2.vhdl b/testsuite/gna/issue150/concat2.vhdl new file mode 100644 index 000000000..b014f102d --- /dev/null +++ b/testsuite/gna/issue150/concat2.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +entity concat is + port (a: in std_ulogic_vector (3 downto 0); + b: in std_ulogic_vector (3 downto 0); + q1: out std_ulogic_vector (7 downto 0); + q2: out std_ulogic_vector (7 downto 0); + q3: out std_ulogic_vector (7 downto 0)); +end concat; + + +architecture rtl of concat is +begin + as_q1: q1 <= "0000" & b; + as_q2: q2 <= a & "0000"; + as_q3: q3 <= a & b; +end rtl; + + |