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author | Tristan Gingold <tgingold@free.fr> | 2021-09-09 17:52:11 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-10 07:34:19 +0200 |
commit | f30826bdd87ac8191cc03f30fd00ba170f0f6c55 (patch) | |
tree | 2864836b355f33a0e89d134b8af1e4942a63a5b6 /testsuite/gna/issue1443 | |
parent | 7dc591471352c5a68eec36b0962d5cae4d47e0b7 (diff) | |
download | ghdl-f30826bdd87ac8191cc03f30fd00ba170f0f6c55.tar.gz ghdl-f30826bdd87ac8191cc03f30fd00ba170f0f6c55.tar.bz2 ghdl-f30826bdd87ac8191cc03f30fd00ba170f0f6c55.zip |
testsuite/gna: add a test for #1443
close #1443
Diffstat (limited to 'testsuite/gna/issue1443')
-rw-r--r-- | testsuite/gna/issue1443/e.vhdl | 23 | ||||
-rwxr-xr-x | testsuite/gna/issue1443/testsuite.sh | 11 |
2 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/gna/issue1443/e.vhdl b/testsuite/gna/issue1443/e.vhdl new file mode 100644 index 000000000..91ee057cf --- /dev/null +++ b/testsuite/gna/issue1443/e.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity e is + port (p1 : out std_logic_vector((3+1)+1 downto 0); + p2 : out std_logic_vector((3-1)+1 downto 0); + p3 : out std_logic_vector((3 )+1 downto 0)); +end e; + +architecture rtl of e is + function f (a : integer) return integer is + begin + return a; + end function; + + signal s1 : std_logic_vector(3+1 downto 0) := (others=>'0'); + signal s2 : std_logic_vector(3-1 downto 0) := (others=>'0'); + signal s3 : std_logic_vector(f(3) downto 0) := (others=>'0'); +begin + p1 <= ('0',s1); + p2 <= ('0',s2); + p3 <= ('0',s3); +end architecture; diff --git a/testsuite/gna/issue1443/testsuite.sh b/testsuite/gna/issue1443/testsuite.sh new file mode 100755 index 000000000..1a4b10413 --- /dev/null +++ b/testsuite/gna/issue1443/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze e.vhdl +elab_simulate e + +clean + +echo "Test successful" |