testsuite/gna: add tests for #1377

3 files changed, 51 insertions, 0 deletions

diff --git a/testsuite/gna/issue1377/tb_issue.vhdl b/testsuite/gna/issue1377/tb_issue.vhdl
new file mode 100644
index 000000000..7fe4cada2
--- /dev/null
+++ b/testsuite/gna/issue1377/tb_issue.vhdl
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity tb_issue is
+end entity tb_issue;
+
+architecture dataflow of tb_issue is
+
+    type ia is
+        array (integer range <>) of std_logic_vector(0 downto 0);
+
+    signal ip : ia(0 to 0) := (others => (others => '0'));
+
+    signal ins : std_logic_vector(1*1-1 downto 0) := (others => '0');
+
+begin
+
+    lbl : for i in 0 to 0 generate
+      ins((i+1)*1-1 downto i*1) <= ip(i);
+      --ins((0+1)*1-1 downto 0*1) <= ip(0); -- works                            
+    end generate;
+
+end architecture dataflow;
diff --git a/testsuite/gna/issue1377/tb_issue2.vhdl b/testsuite/gna/issue1377/tb_issue2.vhdl
new file mode 100644
index 000000000..cb1cef9f9
--- /dev/null
+++ b/testsuite/gna/issue1377/tb_issue2.vhdl
@@ -0,0 +1,18 @@
+entity tb_issue2 is
+end entity tb_issue2;
+
+architecture dataflow of tb_issue2 is
+
+    type ia is array (integer range <>) of bit_vector(0 downto 0);
+
+    signal ip : ia(0 to 0) := (others => (others => '0'));
+
+    signal ins : bit_vector(1 downto 0) := (others => '0');
+
+begin
+
+    lbl : for i in 0 to 0 generate
+      ins(i downto i) <= ip(i);
+    end generate;
+
+end architecture dataflow;
diff --git a/testsuite/gna/issue1377/testsuite.sh b/testsuite/gna/issue1377/testsuite.sh
new file mode 100755
index 000000000..cb4882d08
--- /dev/null
+++ b/testsuite/gna/issue1377/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze -O tb_issue.vhdl
+analyze -O tb_issue2.vhdl
+
+clean
+
+echo "Test successful"