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authorTristan Gingold <tgingold@free.fr>2016-07-29 03:39:52 +0200
committerTristan Gingold <tgingold@free.fr>2016-07-30 07:03:39 +0200
commit91598880d64ed2be9a53c0b6a07c4fdf602e71c1 (patch)
tree25fca7f2eefb433202a71046ecd84bb3fcc38cee /testsuite/gna/issue125/bug.vhdl
parent46e91341fa5eeeb6d678c703d2d041a45d71de8f (diff)
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Add testcase for issue #125
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diff --git a/testsuite/gna/issue125/bug.vhdl b/testsuite/gna/issue125/bug.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+entity ent is end entity;
+architecture a of ent is
+begin
+ process is
+ alias logic is std_ulogic;
+ function fun return string is
+ variable v : std_ulogic_vector(0 to 3);
+ begin
+ if ( v = x"7" ) then return "was 7";
+ else return "not 7"; end if;
+ end function;
+ begin
+ report "yo: " & fun; wait;
+ end process;
+end architecture;