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author | Tristan Gingold <tgingold@free.fr> | 2016-07-29 03:39:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-07-30 07:03:39 +0200 |
commit | 91598880d64ed2be9a53c0b6a07c4fdf602e71c1 (patch) | |
tree | 25fca7f2eefb433202a71046ecd84bb3fcc38cee /testsuite/gna/issue125/bug.vhdl | |
parent | 46e91341fa5eeeb6d678c703d2d041a45d71de8f (diff) | |
download | ghdl-91598880d64ed2be9a53c0b6a07c4fdf602e71c1.tar.gz ghdl-91598880d64ed2be9a53c0b6a07c4fdf602e71c1.tar.bz2 ghdl-91598880d64ed2be9a53c0b6a07c4fdf602e71c1.zip |
Add testcase for issue #125
Diffstat (limited to 'testsuite/gna/issue125/bug.vhdl')
-rw-r--r-- | testsuite/gna/issue125/bug.vhdl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/gna/issue125/bug.vhdl b/testsuite/gna/issue125/bug.vhdl new file mode 100644 index 000000000..9249d9725 --- /dev/null +++ b/testsuite/gna/issue125/bug.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; +entity ent is end entity; +architecture a of ent is +begin + process is + alias logic is std_ulogic; + function fun return string is + variable v : std_ulogic_vector(0 to 3); + begin + if ( v = x"7" ) then return "was 7"; + else return "not 7"; end if; + end function; + begin + report "yo: " & fun; wait; + end process; +end architecture; |