File bug23165.

2 files changed, 73 insertions, 0 deletions

diff --git a/testsuite/gna/bug23165/mwe_failing/counter.vhd b/testsuite/gna/bug23165/mwe_failing/counter.vhd
new file mode 100644
index 000000000..9982f1d6c
--- /dev/null
+++ b/testsuite/gna/bug23165/mwe_failing/counter.vhd
@@ -0,0 +1,33 @@
+-- counter
+-- clk: clock input
+-- en: enable input
+-- rst: reset input
+-- dir: direction pin (1 = up, 0 = down)
+-- q: output
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+	generic (
+		width	: positive := 16
+	);
+
+	port (
+		clk	: in std_logic;
+		q	: out std_logic_vector(width-1 downto 0)
+	);
+end counter;
+
+architecture behav of counter is
+signal cnt	: unsigned(width-1 downto 0) := to_unsigned(0, width);
+begin
+	process
+	begin
+		wait until rising_edge(clk);
+		cnt <= cnt + to_unsigned(1, cnt'length);
+	end process;
+	q <= std_logic_vector(cnt);
+end behav;
+
diff --git a/testsuite/gna/bug23165/mwe_failing/mwe.vhd b/testsuite/gna/bug23165/mwe_failing/mwe.vhd
new file mode 100644
index 000000000..d3241ac03
--- /dev/null
+++ b/testsuite/gna/bug23165/mwe_failing/mwe.vhd
@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mwe is
+end mwe;
+
+architecture lulz of mwe is
+
+constant cnt_len	: integer := 2;
+constant cnt_stages	: integer := 2;
+
+type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
+signal ctl_cnt 	: ctl_sig(0 to cnt_stages-1);
+
+signal clk	: std_logic := '0';
+
+begin
+	clk <= not clk after 50 ns;
+
+	controller : entity work.counter
+	generic map(
+		width => cnt_len
+	)
+	port map(
+		clk => clk,
+		q => ctl_cnt(0)
+	);
+
+	ctl_cnt_delay : process
+	begin
+		wait until rising_edge(clk);
+		for i in 0 to cnt_stages-2 loop
+			-- uncomment following line to see that the port map assignment works
+			--  and that this line just "overwrites" it..
+			ctl_cnt(i+1) <= ctl_cnt(i);
+		end loop;
+	end process;
+
+end lulz;