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authorTristan Gingold <tgingold@free.fr>2014-10-29 20:36:02 +0100
committerTristan Gingold <tgingold@free.fr>2014-10-29 20:36:02 +0100
commit236a876a8448b89061bb71869c36a68aea0199c3 (patch)
tree36f03ad7f2b9a5eec72f3c635f90228f84696cbd /testsuite/gna/bug22868/fails2.vhdl
parente00d31baa0e7190b959cfb03df03b260e402da05 (diff)
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Add testcase for bug 22868.
Diffstat (limited to 'testsuite/gna/bug22868/fails2.vhdl')
-rw-r--r--testsuite/gna/bug22868/fails2.vhdl28
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/gna/bug22868/fails2.vhdl b/testsuite/gna/bug22868/fails2.vhdl
new file mode 100644
index 000000000..57819f9cf
--- /dev/null
+++ b/testsuite/gna/bug22868/fails2.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fails2 is
+ port(
+ x : in std_logic;
+ y : out std_logic_vector(7 downto 0);
+ z : out std_logic
+ );
+end fails2;
+
+architecture a of fails2 is
+ component subcomponent is
+ port(
+ x : in std_logic;
+ y : out std_logic_vector(8 downto 0)
+ );
+ end component;
+begin
+
+ s : subcomponent
+ port map(
+ x => x,
+ y(cheese downto 1) => y,
+ y(0) => z
+ );
+
+end a;