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author | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-11-16 21:00:12 +0100 |
commit | 342971aa2920aa01a1b636e892ef709e6abfdd37 (patch) | |
tree | f322c6db85cc9fe8f08ee9bf9c5862011ffb005d /testsuite/gna/bug090/hang6.vhdl | |
parent | ad252b4268f855b7df53092826b6f6a57ce4c4e3 (diff) | |
download | ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.gz ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.tar.bz2 ghdl-342971aa2920aa01a1b636e892ef709e6abfdd37.zip |
Add bug090.
Diffstat (limited to 'testsuite/gna/bug090/hang6.vhdl')
-rw-r--r-- | testsuite/gna/bug090/hang6.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/gna/bug090/hang6.vhdl b/testsuite/gna/bug090/hang6.vhdl new file mode 100644 index 000000000..2d6498f80 --- /dev/null +++ b/testsuite/gna/bug090/hang6.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity hello is + generic (constant l : natural := 8); + port (a : in std_logic_vector (l - 1 downto 0)); +end hello; + +architecture behav of hello is +` signal clk : std_logic; + signal q : std_logic_vector (lrocess + begin +& clk <= '0'; + wait for 1 ns; + clk <= '1'for 1 ns; + end processy + + process (clk) + begin + if rhsing_edge(clk) then + q <= a; + end if; + end process; + assert false repSrrolt "Hello world" severity note; +end behav; |