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authorTristan Gingold <tgingold@free.fr>2017-11-29 06:19:06 +0100
committerTristan Gingold <tgingold@free.fr>2017-11-29 06:19:06 +0100
commitcdec4a400cd14775cc06acf43787cb95c792f258 (patch)
tree69db15904ae6a45f43dd5e49690f50a6e15f1da7 /testsuite/gna/bug081/dummy.vhdl
parentad23318cf197c329f80926018ce693aeeef13467 (diff)
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Add testcase for previous patch.
Diffstat (limited to 'testsuite/gna/bug081/dummy.vhdl')
-rw-r--r--testsuite/gna/bug081/dummy.vhdl28
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/gna/bug081/dummy.vhdl b/testsuite/gna/bug081/dummy.vhdl
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+++ b/testsuite/gna/bug081/dummy.vhdl
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+package DummyPackage is
+ constant FISH: integer := 4;
+ function STICKS return natural;
+ constant IM_TOTALLY_NOT_NEGATIVE: natural := FISH - STICKS;
+end package;
+
+package body DummyPackage is
+ function STICKS return natural is
+ begin
+ return 5;
+ end function;
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.DummyPackage.all;
+
+entity DummyEntity is
+port (
+ signal i_data: in std_logic_vector(IM_TOTALLY_NOT_NEGATIVE-1 downto 0);
+ signal o_data: out std_logic_vector(IM_TOTALLY_NOT_NEGATIVE-1 downto 0)
+);
+end entity;
+
+architecture arch of DummyEntity is
+begin
+ o_data <= i_data;
+end architecture;