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author | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:46:45 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-10-29 09:49:01 +0100 |
commit | 6ecc19f129a9cb25c9edb0fab18f56f5d0914a40 (patch) | |
tree | 305ce0d6495d010b130fbf7a1bdd9eea859e4906 /testsuite/gna/bug077/repro4.vhdl | |
parent | 6a5dd8aa7565e497b9ec19f6a95dd236a50f1628 (diff) | |
download | ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.gz ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.tar.bz2 ghdl-6ecc19f129a9cb25c9edb0fab18f56f5d0914a40.zip |
Add test cases for individual assocs.
Diffstat (limited to 'testsuite/gna/bug077/repro4.vhdl')
-rw-r--r-- | testsuite/gna/bug077/repro4.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/bug077/repro4.vhdl b/testsuite/gna/bug077/repro4.vhdl new file mode 100644 index 000000000..15eba7260 --- /dev/null +++ b/testsuite/gna/bug077/repro4.vhdl @@ -0,0 +1,26 @@ +entity repro3 is +end repro3; + +architecture behav of repro3 is + type my_rec is record + a : bit; + w : bit_vector; + end record; + + procedure check (v : my_rec) is + begin + assert v = ('0', "10"); + end check; + + procedure pack (a : bit; w : bit_vector) is + begin + check (v.a => a, + v.w => w); + end pack; +begin + process + begin + pack ('0', "01"); + wait; + end process; +end; |