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| author | Tristan Gingold <tgingold@free.fr> | 2020-07-01 21:28:55 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-07-01 21:28:55 +0200 |
| commit | 6bc221560e88b7e5b6977ab0811f48f192db064a (patch) | |
| tree | 73b8ffd20264c2c4e817cc003573c3e57b9a03ae /testsuite/gna/bug0117/repro3.vhdl | |
| parent | 84f15226f84de0f81b60ae7cfdf6abbc52550f8b (diff) | |
| download | ghdl-6bc221560e88b7e5b6977ab0811f48f192db064a.tar.gz ghdl-6bc221560e88b7e5b6977ab0811f48f192db064a.tar.bz2 ghdl-6bc221560e88b7e5b6977ab0811f48f192db064a.zip | |
testsuite/gna: add tests for previous commit.
Diffstat (limited to 'testsuite/gna/bug0117/repro3.vhdl')
| -rw-r--r-- | testsuite/gna/bug0117/repro3.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/gna/bug0117/repro3.vhdl b/testsuite/gna/bug0117/repro3.vhdl new file mode 100644 index 000000000..a17e82843 --- /dev/null +++ b/testsuite/gna/bug0117/repro3.vhdl @@ -0,0 +1,13 @@ +entity repro3 is +end; + +architecture behav of repro3 is + type rec1 is record + wr : bit; + dat : bit_vector(7 downto 0); + end record; + + signal s : rec1; +begin + s <= ('0', x"01"); +end behav; |