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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-12 18:41:32 +0200 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-12 18:41:32 +0200 |
| commit | 26235c3d1e04457801365f9028a1ac3ac58c08a6 (patch) | |
| tree | e8dc3c078cea0a494607b6437ab03ecc76bb78ed /testsuite/gna/bug0101/repro1.vhdl | |
| parent | 6f25e8dff808b37013cf6fa0cb2868e8a85caa79 (diff) | |
| download | ghdl-26235c3d1e04457801365f9028a1ac3ac58c08a6.tar.gz ghdl-26235c3d1e04457801365f9028a1ac3ac58c08a6.tar.bz2 ghdl-26235c3d1e04457801365f9028a1ac3ac58c08a6.zip | |
Add a testcase for previous commit.
Diffstat (limited to 'testsuite/gna/bug0101/repro1.vhdl')
| -rw-r--r-- | testsuite/gna/bug0101/repro1.vhdl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/testsuite/gna/bug0101/repro1.vhdl b/testsuite/gna/bug0101/repro1.vhdl new file mode 100644 index 000000000..cee8c1111 --- /dev/null +++ b/testsuite/gna/bug0101/repro1.vhdl @@ -0,0 +1,10 @@ +entity repro1 is +end repro1; + +architecture behav of repro1 is + signal sig : bit_vector (7 downto 0); +begin + g : for i in sig1'range generate + sig (i) <= sig (i) and '1'; + end generate; +end behav; |