simul: allow unassigned top generics

2 files changed, 9 insertions, 3 deletions

diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 08377c1e1..1e5c0f557 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -79,7 +79,7 @@ package body Ghdlsimul is
       Lib_Unit : Node;
       Inst : Synth_Instance_Acc;
    begin
-      Common_Compile_Elab (Cmd_Name, Args, False, Opt_Arg, Config);
+      Common_Compile_Elab (Cmd_Name, Args, True, Opt_Arg, Config);
 
       for I in Opt_Arg .. Args'Last loop
          if Args (I).all = "--expect-failure" then
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index be7d5a7d5..389a816a4 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -910,11 +910,17 @@ package body Elab.Vhdl_Insts is
             Em : Mark_Type;
             Val : Valtyp;
             Inter_Typ : Type_Acc;
+            Defval : Node;
          begin
             Mark_Expr_Pool (Em);
             Inter_Typ := Elab_Declaration_Type (Top_Inst, Inter);
-            Val := Synth_Expression_With_Type
-              (Top_Inst, Get_Default_Value (Inter), Inter_Typ);
+            Defval := Get_Default_Value (Inter);
+            if Defval /= Null_Node then
+               Val := Synth_Expression_With_Type (Top_Inst, Defval, Inter_Typ);
+            else
+               --  Only for simulation, expect override.
+               Val := Create_Value_Default (Inter_Typ);
+            end if;
             pragma Assert (Is_Static (Val.Val));
             Val := Unshare (Val, Instance_Pool);
             Val.Typ := Unshare_Type_Instance (Val.Typ, Inter_Typ);