Typo fixes in Ada code.

3 files changed, 48 insertions, 48 deletions

diff --git a/src/libraries.ads b/src/libraries.ads
index a4028cdad..688d9251f 100644
--- a/src/libraries.ads
+++ b/src/libraries.ads
@@ -167,7 +167,7 @@ package Libraries is
 
    --  Find an entity whose name is NAME in any library.
    --  If there is no such entity, return NULL_IIR.
-   --  If there are severals entities, return NULL_IIR;
+   --  If there are several entities, return NULL_IIR;
    function Find_Entity_For_Component (Name: Name_Id) return Iir_Design_Unit;
 
    --  Decode '--work=NAME' command line option and return the identifier
@@ -177,7 +177,7 @@ package Libraries is
    --  Return Null_Identifier if NAME is not a valid name.
    function Decode_Work_Option (Opt : String) return Name_Id;
 
-   --  Get the chain of libraries.  Can be used only to read (it musn't be
+   --  Get the chain of libraries.  Can be used only to read (it mustn't be
    --  modified).
    function Get_Libraries_Chain return Iir_Library_Declaration;
 end Libraries;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 93ea74f11..1d1bbda52 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -31,7 +31,7 @@ package Vhdl.Nodes is
    --  but oriented object features are not used, and often, functions
    --  or fields have changed.
 
-   --  Note: this tree is also used during syntaxic analysis, but with
+   --  Note: this tree is also used during syntactic analysis, but with
    --  a little bit different meanings for the fields.
    --  The parser (parse package) build the tree.
    --  The semantic pass (sem, sem_expr, sem_names, ...) transforms it into a
@@ -39,7 +39,7 @@ package Vhdl.Nodes is
 
    --  Documentation:
    --  Only the semantic aspect is to be fully documented.
-   --  The syntaxic aspect is only used between parse and sem.
+   --  The syntactic aspect is only used between parse and sem.
 
    --  Each node of the tree is a record of type iir, based on the private (so
    --  hidden) type nodes.node_type.
@@ -52,7 +52,7 @@ package Vhdl.Nodes is
    --
    --  As the tree represents an AST it is in fact a graph: for there are links
    --  from names to the declaration.  However these links are marked
-   --  explicitely as Ref.  A Ref doesn't own the node.
+   --  explicitly as Ref.  A Ref doesn't own the node.
    --
    --  The distinction between owner and reference is very important as it
    --  allows to use this meta-model for processing: displaying the tree
@@ -70,7 +70,7 @@ package Vhdl.Nodes is
    --  The root of a semantic tree is a library_declaration.
    --  All the library_declarations are kept in a private list, held by
    --  package libraries.
-   --  Exemple of a tree:
+   --  Example of a tree:
    --   library_declaration
    --   +-- design_file
    --       +-- design_unit
@@ -108,14 +108,14 @@ package Vhdl.Nodes is
    --   ...
    --       Iir_Kind_ZZZ
    --      );
-   --  The tool doesn't check for uniqness as this is done by the compiler.
+   --  The tool doesn't check for uniqueness as this is done by the compiler.
    --
    --  It is possible to declare ranges of kinds like this:
    --   subtype Iir_Kinds_RANGE is Iir_Kind range
    --     Iir_Kind_FIRST ..
    --   --Iir_Kind_MID
    --     Iir_Kind_LAST;
-   --  Literals Iir_Kind_MID are optionnal (FIXME: make them required ?), but
+   --  Literals Iir_Kind_MID are optional (FIXME: make them required ?), but
    --  if present all the values between FIRST and LAST must be present.
    --
    --  The methods appear after the comment: '   -- General methods.'
@@ -145,10 +145,10 @@ package Vhdl.Nodes is
    --   --
    --   -- Only for Iir_Kind_NODE1:
    --   --   Get/Set_NAME4 (FIELD3)
-   --  Severals nodes can be described at once; at least one must be described.
+   --  Several nodes can be described at once; at least one must be described.
    --  Fields FIELD1, FIELD2, FIELD3 must be different, unless 'Alias ' is
    --  present.  The number of spaces is significant.  The 'Only for ' lines
-   --  are optionnal and there may be severals of them.
+   --  are optional and there may be several of them.
 
    -------------------------------------------------
    -- General methods (can be used on all nodes): --
@@ -178,7 +178,7 @@ package Vhdl.Nodes is
    -- Start of Iir_Kind.
 
    --------------------------------------------------
-   --  A set of methods are associed with a kind.  --
+   --  A set of methods are associated with a kind.  --
    --------------------------------------------------
 
    -- Iir_Kind_Design_File (Medium)
@@ -250,7 +250,7 @@ package Vhdl.Nodes is
    --
    --  Set the line and the offset in the line, only for the library manager.
    --  This is valid until the file is really loaded in memory.  On loading,
-   --  location will contain all this informations.
+   --  location will contain all this information.
    --   Get/Set_Design_Unit_Source_Pos (Field10)
    --
    --   Get/Set_Design_Unit_Source_Line (Field11)
@@ -281,7 +281,7 @@ package Vhdl.Nodes is
    --  Note: a library_clause node is created for every logical_name.
    --  As a consequence, the scope of the library starts after the logical_name
    --  and not after the library_clause.  However, since an identifier
-   --  can only be used as a logical_name, and since the second occurence has
+   --  can only be used as a logical_name, and since the second occurrence has
    --  no effect, this is correct.
    --
    --   Get/Set_Parent (Field0)
@@ -391,7 +391,7 @@ package Vhdl.Nodes is
    --   Get/Set_Expr_Staticness (State1)
 
    -- Iir_Kind_Simple_Aggregate (Short)
-   --  This node can only be generated by evaluation: it is an unidimentional
+   --  This node can only be generated by evaluation: it is an unidimensional
    --  positional aggregate.
    --
    --  Same as Type, but marked as property of that node.
@@ -873,7 +873,7 @@ package Vhdl.Nodes is
    --
    --   Get/Set_Clock_Expression (Field4)
    --
-   --  Reference to the defult_clock node.
+   --  Reference to the default_clock node.
    --   Get/Set_Default_Clock (Field3)
    --
    --   Get/Set_Expr_Staticness (State1)
@@ -1146,7 +1146,7 @@ package Vhdl.Nodes is
    --
    --   Get/Set_Chain (Field2)
    --
-   --  This node is used to contain all a library.  Only internaly used.
+   --  This node is used to contain all a library.  Only internally used.
    --  Name (identifier) of the library.
    --   Get/Set_Identifier (Field3)
    --
@@ -1155,7 +1155,7 @@ package Vhdl.Nodes is
    --
    --   Get/Set_Library_Directory (Field5)
    --
-   --  Used to compute dependences.
+   --  Used to compute dependencies.
    --   Get/Set_Elab_Flag (Flag3)
    --
    --   Get/Set_Visible_Flag (Flag4)
@@ -1241,7 +1241,7 @@ package Vhdl.Nodes is
    --
    --   Get/Set_Alias_Signature (Field5)
    --
-   --  Set when the alias was implicitely created (by Sem) because of an
+   --  Set when the alias was implicitly created (by Sem) because of an
    --  explicit alias of a type.
    --   Get/Set_Implicit_Alias_Flag (Flag1)
    --
@@ -1553,7 +1553,7 @@ package Vhdl.Nodes is
    --  ignored if there is a subprogram declaration.  The function
    --  Is_Second_Subprogram_Specification returns True on such specification.
    --
-   --  The declaration containing this subrogram declaration.
+   --  The declaration containing this subprogram declaration.
    --   Get/Set_Parent (Field0)
    --
    -- Only for Iir_Kind_Function_Declaration:
@@ -2346,9 +2346,9 @@ package Vhdl.Nodes is
    --  this definition. For some types, such as integer and floating point
    --  types, both type and subtype points to the declaration.
    --  However, there are cases where a type definition doesn't point to
-   --  a declarator: anonymous subtype created by index contraints, or
+   --  a declarator: anonymous subtype created by index constraints, or
    --  anonymous subtype created by an object declaration.
-   --  Note: a type definition cannot be anoynymous.
+   --  Note: a type definition cannot be anonymous.
    --   Get/Set_Type_Declarator (Field3)
    --
    --  The parent type.
@@ -2403,7 +2403,7 @@ package Vhdl.Nodes is
    -- Iir_Kind_Enumeration_Literal (Short)
    --
    --  Nota: two literals of the same type are equal iff their value is the
-   --  same; in other words, there may be severals literals with the same
+   --  same; in other words, there may be several literals with the same
    --  value.
    --
    --  The parent of an enumeration_literal is the same parent as the type
@@ -2741,7 +2741,7 @@ package Vhdl.Nodes is
    --  subtype_indication ::=
    --    [ resolution_indication ] type_mark [ constraint ]
    --
-   --  There is no uniq representation for a subtype indication.  If there is
+   --  There is no unique representation for a subtype indication.  If there is
    --  only a type_mark, then a subtype indication is represented by a name
    --  (a simple name or an expanded name); otherwise it is represented by one
    --  of the subtype definition node.
@@ -3702,7 +3702,7 @@ package Vhdl.Nodes is
    --       { ELSIF condition THEN
    --          sequence_of_statements }
    --       [ ELSE
-   --          sequence_of_satements ]
+   --          sequence_of_statements ]
    --       END IF [ /if/_label ] ;
    --
    --   Get/Set_Parent (Field0)
@@ -4149,7 +4149,7 @@ package Vhdl.Nodes is
    --  Same as Type, but marked as property of that node.
    --   Get/Set_Literal_Subtype (Field3)
    --
-   --  Exist for symetry with other literals, but must never be set.  The
+   --  Exist for symmetry with other literals, but must never be set.  The
    --  content of the aggregate is modified during evaluation, not the
    --  aggregate itself.
    --   Get/Set_Literal_Origin (Field2)
@@ -4175,12 +4175,12 @@ package Vhdl.Nodes is
    --  has no 'others' choice.
    --   Get/Set_Aggr_Dynamic_Flag (Flag3)
    --
-   --  If TRUE, the aggregate is named, else it is positionnal.
+   --  If TRUE, the aggregate is named, else it is positional.
    --   Get/Set_Aggr_Named_Flag (Flag4)
    --
    --  The following three fields are used to check bounds of an array
    --  aggregate.
-   --  For named aggregate, low and high bounds are computed, for positionnal
+   --  For named aggregate, low and high bounds are computed, for positional
    --  aggregate, the (minimum) number of elements is computed.
    --  Note there may be elements beyond the bounds, due to other choice.
    --  These fields may apply for the aggregate or for the aggregate and its
@@ -4451,7 +4451,7 @@ package Vhdl.Nodes is
    --   Get/Set_Is_Forward_Ref (Flag1)
 
    -- Iir_Kind_Selected_Element (Short)
-   --  A record element selection.  This corresponds to a reffined selected
+   --  A record element selection.  This corresponds to a refined selected
    --  names.  The production doesn't exist in the VHDL grammar.
    --
    --   Get/Set_Prefix (Field0)
@@ -5211,7 +5211,7 @@ package Vhdl.Nodes is
    --  Get_Has_Mode: set if mode is explicit
    --  has_class: set if class (constant, signal, variable or file) is explicit
    --
-   --  Exemple:
+   --  Example:
    --  procedure P (         A, B:       integer;
    --               constant C:    in    bit;
    --                        D:    inout bit;
@@ -5987,7 +5987,7 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Std_Logic_Signed_Shl,
       Iir_Predefined_Ieee_Std_Logic_Signed_Shr,
 
-      --  std_logic_arith (synopsys extention).
+      --  std_logic_arith (synopsys extension).
       Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int,
       Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns,
       Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn,
@@ -6211,7 +6211,7 @@ package Vhdl.Nodes is
      Iir_Predefined_Error ..
      Iir_Predefined_Functions'Pred (Iir_Predefined_None);
 
-   --  Subtype for exlicit subprograms.  These require a corresponding body.
+   --  Subtype for explicit subprograms.  These require a corresponding body.
    subtype Iir_Predefined_Explicit is Iir_Predefined_Functions range
      Iir_Predefined_None ..
      Iir_Predefined_Functions'Last;
@@ -6294,7 +6294,7 @@ package Vhdl.Nodes is
       Fully_Constrained
      );
 
-   --  The kind of an inteface list.
+   --  The kind of an interface list.
    type Interface_Kind_Type is
      (
       Generic_Interface_List,
@@ -6315,7 +6315,7 @@ package Vhdl.Nodes is
    ---------------
    -- subranges --
    ---------------
-   -- These subtypes are used for ranges, for `case' statments or for the `in'
+   -- These subtypes are used for ranges, for `case' statements or for the `in'
    -- operator.
 
    -- In order to be correctly parsed by check_iir, the declaration must
@@ -7024,7 +7024,7 @@ package Vhdl.Nodes is
       Date_Extern,
 
       --  The unit is not loaded (still on the disk).
-      --  All the informations come from the library file.
+      --  All the information come from the library file.
       Date_Disk,
 
       --  The unit has been parsed, but not analyzed.
@@ -7041,7 +7041,7 @@ package Vhdl.Nodes is
 
    --  The unit is obsoleted (ie replaced) by a more recently analyzed design
    --  unit.
-   --  If another design unit depends (directly or not) on an obseleted design
+   --  If another design unit depends (directly or not) on an obsoleted design
    --  unit, it is also obsolete, and cannot be defined.
    Date_Obsolete      : constant Date_Type := 0;
    --  A unit with the same name (could also be the same unit) is being
@@ -7457,7 +7457,7 @@ package Vhdl.Nodes is
    --  If TRUE, the target of the signal assignment is guarded.
    --  If FALSE, the target is not guarded.
    --  This is determined during sem by examining the declaration(s) of the
-   --  target (there may be severals declarations in the case of a aggregate
+   --  target (there may be several declarations in the case of a aggregate
    --  target).
    --  If UNKNOWN, this is not determined at compile time but at run-time.
    --  This is the case for formal signal interfaces of subprograms.
@@ -7479,7 +7479,7 @@ package Vhdl.Nodes is
 
    -- Set the line and the offset in the line, only for the library manager.
    -- This is valid until the file is really loaded in memory.  On loading,
-   -- location will contain all this informations.
+   -- location will contain all this information.
    --  Field: Field10 (uc)
    function Get_Design_Unit_Source_Pos (Design_Unit : Iir) return Source_Ptr;
    procedure Set_Design_Unit_Source_Pos (Design_Unit : Iir; Pos : Source_Ptr);
@@ -7848,7 +7848,7 @@ package Vhdl.Nodes is
    function Get_Subtype_Indication (Target : Iir) return Iir;
    procedure Set_Subtype_Indication (Target : Iir; Atype : Iir);
 
-   --  Discrete range of an iterator.  During analysis, a subtype indiciation
+   --  Discrete range of an iterator.  During analysis, a subtype indication
    --  is created from this range.
    --  Field: Field4
    function Get_Discrete_Range (Target : Iir) return Iir;
@@ -7948,9 +7948,9 @@ package Vhdl.Nodes is
    procedure Set_Overload_Number (Target : Iir; Val : Iir_Int32);
 
    --  Depth of a subprogram.
-   --  For a subprogram declared immediatly within an entity, architecture,
+   --  For a subprogram declared immediately within an entity, architecture,
    --  package, process, block, generate, the depth is 0.
-   --  For a subprogram declared immediatly within a subprogram of level N,
+   --  For a subprogram declared immediately within a subprogram of level N,
    --  the depth is N + 1.
    --  Depth is used with depth of impure objects to check purity rules.
    --  Field: Field10 (pos)
@@ -7958,7 +7958,7 @@ package Vhdl.Nodes is
    procedure Set_Subprogram_Depth (Target : Iir; Depth : Iir_Int32);
 
    --  Hash of a subprogram profile.
-   --  This is used to speed up subprogram profile comparaison, which is very
+   --  This is used to speed up subprogram profile comparison, which is very
    --  often used by overload.
    --  Field: Field4 (pos)
    function Get_Subprogram_Hash (Target : Iir) return Iir_Int32;
@@ -8472,7 +8472,7 @@ package Vhdl.Nodes is
    procedure Set_Pure_Flag (Func : Iir; Flag : Boolean);
 
    --  Get/Set the foreign flag of a declaration.
-   --  TRUE if the declaration was decored with the std.foreign attribute.
+   --  TRUE if the declaration was decorated with the std.foreign attribute.
    --  Field: Flag3
    function Get_Foreign_Flag (Decl : Iir) return Boolean;
    procedure Set_Foreign_Flag (Decl : Iir; Flag : Boolean);
@@ -8708,12 +8708,12 @@ package Vhdl.Nodes is
    function Get_Loop_Label (Target : Iir) return Iir;
    procedure Set_Loop_Label (Target : Iir; Stmt : Iir);
 
-   --  True if there is an exit statement targetting this loop statement.
+   --  True if there is an exit statement targeting this loop statement.
    --  Field: Flag1
    function Get_Exit_Flag (Stmt : Iir) return Boolean;
    procedure Set_Exit_Flag (Stmt : Iir; Flag : Boolean);
 
-   --  True if there is a next statement targetting this loop statement.
+   --  True if there is a next statement targeting this loop statement.
    --  Field: Flag2
    function Get_Next_Flag (Stmt : Iir) return Boolean;
    procedure Set_Next_Flag (Stmt : Iir; Flag : Boolean);
@@ -8878,7 +8878,7 @@ package Vhdl.Nodes is
    --  Type of the actual for an association by individual.
    --    Unless the formal is an unconstrained array type, this is the same as
    --    the formal type.
-   --  Subtype indiciation for a type association.
+   --  Subtype indication for a type association.
    --  Field: Field5 Ref
    function Get_Actual_Type (Target : Iir) return Iir;
    procedure Set_Actual_Type (Target : Iir; Atype : Iir);
@@ -8977,7 +8977,7 @@ package Vhdl.Nodes is
    function Get_Implementation (Target : Iir) return Iir;
    procedure Set_Implementation (Target : Iir; Decl : Iir);
 
-   --  Paramater associations for procedure and function call.
+   --  Parameter associations for procedure and function call.
    --  Field: Field2 Chain
    function Get_Parameter_Association_Chain (Target : Iir) return Iir;
    procedure Set_Parameter_Association_Chain (Target : Iir; Chain : Iir);
@@ -9071,7 +9071,7 @@ package Vhdl.Nodes is
    function Get_Protected_Type_Body (Target : Iir) return Iir;
    procedure Set_Protected_Type_Body (Target : Iir; Bod : Iir);
 
-   --  Corresponsing protected type declaration of a protected type body.
+   --  Corresponding protected type declaration of a protected type body.
    --  Field: Field4 Ref
    function Get_Protected_Type_Declaration (Target : Iir) return Iir;
    procedure Set_Protected_Type_Declaration (Target : Iir; Decl : Iir);
diff --git a/src/vhdl/vhdl-std_package.ads b/src/vhdl/vhdl-std_package.ads
index 144dff066..7b897df10 100644
--- a/src/vhdl/vhdl-std_package.ads
+++ b/src/vhdl/vhdl-std_package.ads
@@ -30,7 +30,7 @@ package Vhdl.Std_Package is
    Std_Source_File : Source_File_Entry := No_Source_File_Entry;
    Std_Location: Location_Type := Location_Nil;
 
-   -- Some well know values declared in the STANDARD package.
+   -- Some well known values declared in the STANDARD package.
    -- These values (except time_base) *must* not be modified, and are set by
    -- create_std_standard_package.