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author | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:55:03 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:55:03 +0200 |
commit | e29e6689ae17bc6669a1a8773968ea79adeaf8ca (patch) | |
tree | 9e0eb2b703557e2dec45231bc84c5c7203ead2c5 /src | |
parent | 4bd6d595d65458e4cf56d8e896092757bb544e0b (diff) | |
download | ghdl-e29e6689ae17bc6669a1a8773968ea79adeaf8ca.tar.gz ghdl-e29e6689ae17bc6669a1a8773968ea79adeaf8ca.tar.bz2 ghdl-e29e6689ae17bc6669a1a8773968ea79adeaf8ca.zip |
synth: fix mul sgn sgn width.
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/synth-expr.adb | 1 | ||||
-rw-r--r-- | src/synth/synth-oper.adb | 16 |
2 files changed, 9 insertions, 8 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 1c085b1c8..d534b5d87 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -1534,6 +1534,7 @@ package body Synth.Expr is N := Build_Extract (Build_Context, Get_Net (Res), Res.Typ.Rec.E (Idx + 1).Off, Get_Type_Width (Res_Typ)); + Set_Location (N, Expr); return Create_Value_Net (N, Res_Typ); end if; end; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 37dae98e6..50449dac6 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -259,10 +259,10 @@ package body Synth.Oper is function Synth_Vec_Dyadic (Id : Dyadic_Module_Id) return Value_Acc is - L : constant Net := Get_Net (Left); N : Net; begin - N := Build_Dyadic (Build_Context, Id, L, Get_Net (Right)); + N := Build_Dyadic (Build_Context, Id, + Get_Net (Left), Get_Net (Right)); Set_Location (N, Expr); return Create_Value_Net (N, Create_Res_Bound (Left)); end Synth_Vec_Dyadic; @@ -513,16 +513,16 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn => declare - L : constant Net := Get_Net (Left); - R : constant Net := Get_Net (Right); - W : constant Width := Get_Width (L) + Get_Width (R); - Rtype : Type_Acc; + W : constant Width := Left.Typ.W + Right.Typ.W; + L, R : Net; N : Net; begin - Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El); + L := Synth_Sresize (Left, W, Left_Expr); + R := Synth_Sresize (Right, W, Right_Expr); N := Build_Dyadic (Build_Context, Id_Smul, L, R); Set_Location (N, Expr); - return Create_Value_Net (N, Rtype); + return Create_Value_Net + (N, Create_Vec_Type_By_Length (W, Left.Typ.Vec_El)); end; when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => declare |