elab-vhdl_expr: fix a crash on simple aggregates. Fix #2240

2 files changed, 13 insertions, 15 deletions

diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index a417f08a6..64c1a176a 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -63,35 +63,32 @@ package body Elab.Vhdl_Expr is
    function Exec_Simple_Aggregate (Syn_Inst : Synth_Instance_Acc;
                                    Aggr : Node) return Valtyp
    is
-      Aggr_Type : constant Node := Get_Type (Aggr);
-      pragma Assert (Get_Nbr_Dimensions (Aggr_Type) = 1);
-      El_Type : constant Node := Get_Element_Subtype (Aggr_Type);
-      El_Typ : constant Type_Acc := Get_Subtype_Object (Syn_Inst, El_Type);
       Els : constant Iir_Flist := Get_Simple_Aggregate_List (Aggr);
       Last : constant Natural := Flist_Last (Els);
-      Bnd : Bound_Type;
-      Res_Type : Type_Acc;
+      Aggr_Type : Node;
+      Res_Typ : Type_Acc;
       Val : Valtyp;
       Res : Valtyp;
    begin
       --  Allocate the result.
-      Bnd := Synth_Array_Bounds (Syn_Inst, Aggr_Type, 1);
-      pragma Assert (Bnd.Len = Uns32 (Last + 1));
-
-      if El_Typ.Kind in Type_Nets then
-         Res_Type := Create_Vector_Type (Bnd, El_Typ);
+      Aggr_Type := Get_Literal_Subtype (Aggr);
+      if Aggr_Type /= Null_Node then
+         Res_Typ := Synth_Subtype_Indication (Syn_Inst, Aggr_Type);
       else
-         Res_Type := Create_Array_Type (Bnd, True, El_Typ);
+         Aggr_Type := Get_Type (Aggr);
+         Res_Typ := Get_Subtype_Object (Syn_Inst, Aggr_Type);
       end if;
+      pragma Assert (Get_Nbr_Dimensions (Aggr_Type) = 1);
+      pragma Assert (Res_Typ.Abound.Len = Uns32 (Last + 1));
 
-      Res := Create_Value_Memory (Res_Type, Current_Pool);
+      Res := Create_Value_Memory (Res_Typ, Current_Pool);
 
       for I in Flist_First .. Last loop
          --  Elements are supposed to be static, so no need for enable.
          Val := Synth_Expression_With_Type
-           (Syn_Inst, Get_Nth_Element (Els, I), El_Typ);
+           (Syn_Inst, Get_Nth_Element (Els, I), Res_Typ.Arr_El);
          pragma Assert (Is_Static (Val.Val));
-         Write_Value (Res.Val.Mem + Size_Type (I) * El_Typ.Sz, Val);
+         Write_Value (Res.Val.Mem + Size_Type (I) * Res_Typ.Arr_El.Sz, Val);
       end loop;
 
       return Res;
diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb
index b3ec1fed5..546fd79a2 100644
--- a/src/synth/elab-vhdl_types.adb
+++ b/src/synth/elab-vhdl_types.adb
@@ -246,6 +246,7 @@ package body Elab.Vhdl_Types is
       El_Typ := Get_Subtype_Object (Syn_Inst, El_Type);
 
       if El_Typ.Kind in Type_Nets and then Ndims = 1 then
+         --  An array of nets is a vector.
          Idx := Get_Index_Type (Def, 0);
          Idx_Typ := Get_Subtype_Object (Syn_Inst, Idx);
          Typ := Create_Unbounded_Vector (El_Typ, Idx_Typ);