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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-25 08:24:44 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-25 08:24:44 +0100 |
| commit | c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d (patch) | |
| tree | 8ddd12121ebc3231d5c03b3e7b38675cd37db901 /src | |
| parent | 383aa041762b77aea45c12d10c8d4178597b0fb8 (diff) | |
| download | ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.tar.gz ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.tar.bz2 ghdl-c2168c679ca3d634d7bdb7b1ca2fcb198d100b6d.zip | |
synth: improve support of 0-width nets and gates. Fix #1113
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-builders.adb | 2 | ||||
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 36 | ||||
| -rw-r--r-- | src/synth/netlists-expands.adb | 1 | ||||
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 10 |
4 files changed, 30 insertions, 19 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index d869ebeba..c205ef318 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -1069,9 +1069,7 @@ package body Netlists.Builders is (Ctxt : Context_Acc; I : Net; Step : Uns32; Max : Uns32; W : Width) return Net is - pragma Assert (Get_Width (I) /= No_Width); pragma Assert (Step > 0); - pragma Assert (W > 0); Inst : Instance; O : Net; begin diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 398e29a16..1458c8cad 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -812,18 +812,22 @@ package body Netlists.Disp_Vhdl is Wd : constant Width := Get_Width (O); Off : constant Uns32 := Get_Param_Uns32 (Inst, 0); begin - Disp_Template (" \o0 <= \i0 (to_integer (\ui1)", Inst); - if Off /= 0 then - Disp_Template (" + \n0", Inst, (0 => Off)); - end if; - if Wd > 1 then - Disp_Template (" + \n0 - 1 downto to_integer (\ui1)", - Inst, (0 => Wd)); + Disp_Template (" \o0 <= \i0", Inst); + if Wd /= 0 then + Disp_Template (" (to_integer (\ui1)", Inst); if Off /= 0 then Disp_Template (" + \n0", Inst, (0 => Off)); end if; + if Wd > 1 then + Disp_Template (" + \n0 - 1 downto to_integer (\ui1)", + Inst, (0 => Wd)); + if Off /= 0 then + Disp_Template (" + \n0", Inst, (0 => Off)); + end if; + end if; + Put (")"); end if; - Put_Line (");"); + Put_Line (";"); end; when Id_Dyn_Insert | Id_Dyn_Insert_En => @@ -1040,13 +1044,17 @@ package body Netlists.Disp_Vhdl is declare W : constant Width := Get_Width (Get_Output (Inst, 0)); begin - Disp_Template (" \o0 <= \i0 ", Inst); - if W = 1 then - Disp_Template ("(0)", Inst); - elsif W = 0 then - Disp_Template ("(-1 downto 0)", Inst); + if W = 0 then + Disp_Template (" \o0 <= """"", Inst); else - Disp_Template ("(\n0 downto 0)", Inst, (0 => W - 1)); + Disp_Template (" \o0 <= \i0 ", Inst); + if W = 1 then + Disp_Template ("(0)", Inst); + elsif W = 0 then + Disp_Template ("(-1 downto 0)", Inst); + else + Disp_Template ("(\n0 downto 0)", Inst, (0 => W - 1)); + end if; end if; Disp_Template ("; -- trunc" & NL, Inst); end; diff --git a/src/synth/netlists-expands.adb b/src/synth/netlists-expands.adb index 3eeee7d3b..734aee64a 100644 --- a/src/synth/netlists-expands.adb +++ b/src/synth/netlists-expands.adb @@ -73,7 +73,6 @@ package body Netlists.Expands is P := P - 1; Max := Get_Param_Uns32 (Memidx, 1); - pragma Assert (Max /= 0); Nbr_Els := Nbr_Els * Natural (Max + 1); exit when Memidx = Ninst; diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 43392147c..c5260bf5a 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -152,13 +152,19 @@ package body Synth.Disp_Vhdl is elsif Is_Std_Logic_Array (Btype) then W := Typ.Vbound.Len; Disp_In_Lhs (Mname, Off, W, Full); - Put ("std_logic_vector(" & Pfx); + if W > 1 then + Put ("std_logic_vector("); + end if; + Put (Pfx); if W = 1 then -- This is an array of length 1. A scalar is used in the -- netlist. Put (" (" & Pfx & "'left)"); end if; - Put_Line (");"); + if W > 1 then + Put (')'); + end if; + Put_Line (";"); elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then W := Typ.Vbound.Len; Disp_In_Lhs (Mname, Off, W, Full); |