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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:27:42 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:27:42 +0100 |
| commit | bad1f59fe02347828cb2d15a74d356320937d952 (patch) | |
| tree | 1c1d0db3709ebc8069ea1c6f99e8a598b2984969 /src | |
| parent | e8a7ea346624d9e6606e354fe44f59f6ffca8dc4 (diff) | |
| download | ghdl-bad1f59fe02347828cb2d15a74d356320937d952.tar.gz ghdl-bad1f59fe02347828cb2d15a74d356320937d952.tar.bz2 ghdl-bad1f59fe02347828cb2d15a74d356320937d952.zip | |
netlists: add more support for dyn_insert_en
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 23 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 3 | ||||
| -rw-r--r-- | src/synth/synth-inference.adb | 1 |
3 files changed, 21 insertions, 6 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 702945c3e..e49165691 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -695,6 +695,7 @@ package body Netlists.Disp_Vhdl is is Imod : constant Module := Get_Module (Inst); Loc : constant Location_Type := Locations.Get_Location (Inst); + Id : constant Module_Id := Get_Id (Imod); begin if Loc /= No_Location then declare @@ -712,7 +713,7 @@ package body Netlists.Disp_Vhdl is New_Line; end; end if; - case Get_Id (Imod) is + case Id is when Id_Memory | Id_Memory_Init => Disp_Memory (Inst); @@ -794,7 +795,8 @@ package body Netlists.Disp_Vhdl is end if; Put_Line (");"); end; - when Id_Dyn_Insert => + when Id_Dyn_Insert + | Id_Dyn_Insert_En => declare -- I0: Input, I1: Value, I2: position -- P0: offset @@ -822,9 +824,13 @@ package body Netlists.Disp_Vhdl is Put (")" & NL); Disp_Template (" begin" & NL & - " \o0 <= \i0;" & NL & - " \o0 (", + " \o0 <= \i0;" & NL, Inst); + if Id = Id_Dyn_Insert_En then + Disp_Template (" if \i3 = '1' then" & NL, Inst); + end if; + Disp_Template + (" \o0 (", Inst); if Iw > 1 then Disp_Template ("to_integer (\ui2) + (\sp0 + \n0)" & NL & @@ -833,8 +839,13 @@ package body Netlists.Disp_Vhdl is end if; Disp_Template ("to_integer (\ui2) + (\sp0))" & - " <= \i1;" & NL & - " end process;" & NL, + " <= \i1;" & NL, + Inst); + if Id = Id_Dyn_Insert_En then + Disp_Template (" end if;" & NL, Inst); + end if; + Disp_Template + (" end process;" & NL, Inst); end; when Id_Const_UB32 diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 53c6ad92d..f5b7e0492 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -160,6 +160,9 @@ package Netlists.Gates is -- Input3: enable Id_Dyn_Insert_En : constant Module_Id := 71; + subtype Dyn_Insert_Module_Id is + Module_Id range Id_Dyn_Insert .. Id_Dyn_Insert_En; + -- OUT := IN0 * STEP, IN0 < MAX Id_Memidx : constant Module_Id := 72; diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index 30aa7ac21..4c4b95c5f 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -265,6 +265,7 @@ package body Synth.Inference is -- Walk the And-net N, and extract clock (posedge/negedge) if found. -- ENABLE is N without the clock. + -- If not found, CLK and ENABLE are set to No_Net. procedure Extract_Clock (Ctxt : Context_Acc; N : Net; Clk : out Net; Enable : out Net) is |