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| author | tgingold <tgingold@users.noreply.github.com> | 2022-07-05 18:10:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-05 18:10:20 +0200 |
| commit | ad14451e079b5762a3987ee0f15bbd0204308bd7 (patch) | |
| tree | 698c47e45de6d69b671696e8c0036d8bcfaaf92f /src | |
| parent | 81bcef85ce7bdc91b32ab223253ff35b7b44c001 (diff) | |
| parent | a5ff910722bbe81d3c8e314732eceb14c72812af (diff) | |
| download | ghdl-ad14451e079b5762a3987ee0f15bbd0204308bd7.tar.gz ghdl-ad14451e079b5762a3987ee0f15bbd0204308bd7.tar.bz2 ghdl-ad14451e079b5762a3987ee0f15bbd0204308bd7.zip | |
Merge pull request #2127 from C-Elegans/to_ux01_unhandled_function
Fix issue #2126, add handling of to_ux01 to synthesis
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 919d1f64e..4a2f4d71e 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1969,7 +1969,8 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn - | Iir_Predefined_Ieee_1164_To_X01_Slv => + | Iir_Predefined_Ieee_1164_To_X01_Slv + | Iir_Predefined_Ieee_1164_To_UX01_Slv => if Is_Static (L.Val) then raise Internal_Error; end if; @@ -1977,6 +1978,7 @@ package body Synth.Vhdl_Oper is return Create_Value_Net (Get_Net (Ctxt, L), Create_Res_Bound (L)); when Iir_Predefined_Ieee_1164_To_Bit | Iir_Predefined_Ieee_1164_To_X01_Log + | Iir_Predefined_Ieee_1164_To_UX01_Log | Iir_Predefined_Ieee_1164_To_Stdulogic => -- A no-op. return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ); |