diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-11-12 18:44:58 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-12 20:36:02 +0100 |
| commit | a6732f023ae5eada414ce69e97d4d93a871431dd (patch) | |
| tree | 0e512c4eff591db93bfbd31cc47d935cb82d68a4 /src | |
| parent | 6d897ec95e89982f6449c083353b8af73c2c0479 (diff) | |
| download | ghdl-a6732f023ae5eada414ce69e97d4d93a871431dd.tar.gz ghdl-a6732f023ae5eada414ce69e97d4d93a871431dd.tar.bz2 ghdl-a6732f023ae5eada414ce69e97d4d93a871431dd.zip | |
synth-disp_vhdl: handle arrays for in-converters.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index 319f42f05..0227e4f2d 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -160,7 +160,26 @@ package body Synth.Disp_Vhdl is Put ("to_stdlogicvector (" & Pfx & ")"); Put_Line (";"); else - Error_Kind ("disp_in_converter(arr)", Ptype); + -- Any array. + declare + Bnd : Bound_Type renames Typ.Abounds.D (1); + El_Type : constant Node := Get_Element_Subtype (Ptype); + El_W : constant Width := Get_Type_Width (Typ.Arr_El); + Idx : Int32; + begin + for I in 0 .. Bnd.Len - 1 loop + case Bnd.Dir is + when Iir_To => + Idx := Bnd.Left + Int32 (I); + when Iir_Downto => + Idx := Bnd.Left - Int32 (I); + end case; + Disp_In_Converter + (Mname, + Pfx & " (" & Int32'Image (Idx) & ")", + Off + I * El_W, El_Type, Typ.Arr_El, False); + end loop; + end; end if; when Iir_Kind_Record_Type_Definition => declare |