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| author | Tristan Gingold <tgingold@free.fr> | 2018-11-16 20:30:58 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-11-16 20:30:58 +0100 |
| commit | 9624f0ce08849f8cf14fe81416496417b4754d9d (patch) | |
| tree | 3414b4f0dce6ca3834d6c24480f5d3f997aedbdd /src | |
| parent | 9e29a2867545769b26aba2264303056bbf423f83 (diff) | |
| download | ghdl-9624f0ce08849f8cf14fe81416496417b4754d9d.tar.gz ghdl-9624f0ce08849f8cf14fe81416496417b4754d9d.tar.bz2 ghdl-9624f0ce08849f8cf14fe81416496417b4754d9d.zip | |
sem: clear default PSL clock at beginning of architecture.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/sem.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb index 7408d05e7..ecb6377af 100644 --- a/src/vhdl/sem.adb +++ b/src/vhdl/sem.adb @@ -204,7 +204,10 @@ package body Sem is if Vhdl_Std = Vhdl_02 then Open_Declarative_Region; end if; + + Current_Psl_Default_Clock := Null_Iir; Sem_Block (Arch); + if Vhdl_Std = Vhdl_02 then Close_Declarative_Region; end if; |