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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-25 19:53:51 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-25 19:53:51 +0100 |
| commit | 81d429db97a76f5128788d1328ead447b4435b2c (patch) | |
| tree | c85995d12c875369eff96614203d9455fea7adc0 /src | |
| parent | 2f8ca2c8e452c3321386a6be04ae24d5369fe148 (diff) | |
| download | ghdl-81d429db97a76f5128788d1328ead447b4435b2c.tar.gz ghdl-81d429db97a76f5128788d1328ead447b4435b2c.tar.bz2 ghdl-81d429db97a76f5128788d1328ead447b4435b2c.zip | |
synth-environment: fix incorrect memory access.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-environment.adb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index af6dd55c1..b32ebfe49 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -451,7 +451,7 @@ package body Synth.Environment is Phi : Phi_Type; Mark : Wire_Id) is - Asgn : Seq_Assign; + Asgn, Next_Asgn : Seq_Assign; begin Asgn := Phi.First; while Asgn /= No_Seq_Assign loop @@ -460,6 +460,10 @@ package body Synth.Environment is Wid : constant Wire_Id := Asgn_Rec.Id; Pasgn, Next_Pasgn : Partial_Assign; begin + -- FIXME: Asgn_Rec may become invalid due to allocation by + -- Phi_Assign. So we read what is needed before calling + -- Phi_Assign. + Next_Asgn := Asgn_Rec.Chain; if Wid <= Mark then Pasgn := Asgn_Rec.Asgns; while Pasgn /= No_Partial_Assign loop @@ -469,7 +473,7 @@ package body Synth.Environment is Pasgn := Next_Pasgn; end loop; end if; - Asgn := Asgn_Rec.Chain; + Asgn := Next_Asgn; end; end loop; end Propagate_Phi_Until_Mark; |