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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-07 19:03:05 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-09 06:40:16 +0100 |
| commit | 816cdc7faae1d4c7651546165e21ae10372f3cbf (patch) | |
| tree | 1317da5ca3040bc7f2c1f6287ffc7675ba176550 /src | |
| parent | 95231d681ebb1072debdeb52cd5c1b052876b299 (diff) | |
| download | ghdl-816cdc7faae1d4c7651546165e21ae10372f3cbf.tar.gz ghdl-816cdc7faae1d4c7651546165e21ae10372f3cbf.tar.bz2 ghdl-816cdc7faae1d4c7651546165e21ae10372f3cbf.zip | |
simul: handle function calls in sensitivity compute.
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 95c144473..2e7f40f7f 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -565,10 +565,14 @@ package body Simul.Vhdl_Elab is El : Node; Sig : Sub_Signal_Type; begin + -- There can be function calls. + Instance_Pool := Process_Pool'Access; + It := List_Iterate_Safe (List); while Is_Valid (It) loop El := Get_Element (It); exit when El = Null_Node; + Sig := Compute_Sub_Signal (Inst, El); -- Exit now in case of error. @@ -587,6 +591,8 @@ package body Simul.Vhdl_Elab is Next (It); end loop; + + Instance_Pool := null; end Gather_Sensitivity; procedure Gather_Process_Sensitivity |