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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:47:00 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 20:47:00 +0100 |
| commit | 7de4670eaaf229205ece2de7d0af733fd863e6fa (patch) | |
| tree | 786ae2be7d7a6a99916012cf2fe117023a9b2131 /src | |
| parent | 9867eb89230df9bf5f02e9d35d0ec478c6f63f0b (diff) | |
| download | ghdl-7de4670eaaf229205ece2de7d0af733fd863e6fa.tar.gz ghdl-7de4670eaaf229205ece2de7d0af733fd863e6fa.tar.bz2 ghdl-7de4670eaaf229205ece2de7d0af733fd863e6fa.zip | |
vhdl: recognize mod/rem operators.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 40 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 14 |
2 files changed, 54 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 990f74b5e..f03ac61d4 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -112,6 +112,42 @@ package body Vhdl.Ieee.Numeric is (others => (others => Iir_Predefined_None))); + Rem_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Rem_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Rem_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + + Mod_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Mod_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Mod_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + Eq_Patterns : constant Binary_Pattern_Type := (Pkg_Std => (Type_Unsigned => @@ -741,6 +777,10 @@ package body Vhdl.Ieee.Numeric is Handle_Binary (Mul_Patterns); when Name_Op_Div => Handle_Binary (Div_Patterns); + when Name_Mod => + Handle_Binary (Mod_Patterns); + when Name_Rem => + Handle_Binary (Rem_Patterns); when Name_Op_Equality => Handle_Binary (Eq_Patterns); when Name_Op_Inequality => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index a9ba20275..54fba3db2 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5527,6 +5527,20 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Div_Sgn_Int, Iir_Predefined_Ieee_Numeric_Std_Div_Int_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Rem_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Std_Rem_Nat_Uns, + Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Rem_Sgn_Int, + Iir_Predefined_Ieee_Numeric_Std_Rem_Int_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Mod_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Std_Mod_Nat_Uns, + Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Mod_Sgn_Int, + Iir_Predefined_Ieee_Numeric_Std_Mod_Int_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Uns, Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Nat, Iir_Predefined_Ieee_Numeric_Std_Gt_Nat_Uns, |