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| author | Tristan Gingold <tgingold@free.fr> | 2016-02-08 20:47:09 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-02-10 07:52:52 +0100 |
| commit | 7b14b0a3fdcd291bd393d157099026cae8a40d3e (patch) | |
| tree | 0beeb065db4c7a3c7eed0faee432b4f47805f06b /src | |
| parent | 45dba464bc2f69145753e4c9c9b1dde0868ec878 (diff) | |
| download | ghdl-7b14b0a3fdcd291bd393d157099026cae8a40d3e.tar.gz ghdl-7b14b0a3fdcd291bd393d157099026cae8a40d3e.tar.bz2 ghdl-7b14b0a3fdcd291bd393d157099026cae8a40d3e.zip | |
simul: fix elaboration check for implicit signals.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/elaboration.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 234fd136a..a183916f3 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -157,6 +157,7 @@ package body Elaboration is T := Execute_Time_Attribute (Instance, Signal); Init := Create_B1_Value (False); end if; + Create_Signal (Instance, Signal); Sig := Create_Signal_Value (null); Init := Unshare (Init, Global_Pool'Access); Instance.Objects (Info.Slot) := Sig; |