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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-10 07:24:27 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:28:41 +0100 |
| commit | 6eb11dd7c637659881f80cd66e5504b2b057d370 (patch) | |
| tree | 76baa3f4e11e3f29da3b41c52d4a87ab6a0ad934 /src | |
| parent | 72094d312400368dda79e32b4403d0f142404fad (diff) | |
| download | ghdl-6eb11dd7c637659881f80cd66e5504b2b057d370.tar.gz ghdl-6eb11dd7c637659881f80cd66e5504b2b057d370.tar.bz2 ghdl-6eb11dd7c637659881f80cd66e5504b2b057d370.zip | |
netlists: expand dyn_insert_en
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 1 | ||||
| -rw-r--r-- | src/synth/netlists-expands.adb | 21 |
2 files changed, 18 insertions, 4 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index e49165691..f673a69de 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -827,6 +827,7 @@ package body Netlists.Disp_Vhdl is " \o0 <= \i0;" & NL, Inst); if Id = Id_Dyn_Insert_En then + -- TODO: fix indentation. Disp_Template (" if \i3 = '1' then" & NL, Inst); end if; Disp_Template diff --git a/src/synth/netlists-expands.adb b/src/synth/netlists-expands.adb index c6f2196e2..3eeee7d3b 100644 --- a/src/synth/netlists-expands.adb +++ b/src/synth/netlists-expands.adb @@ -261,7 +261,8 @@ package body Netlists.Expands is Off : in out Uns32; Dat : Net; Memidx_Arr : Memidx_Array_Type; - Net_Arr : Net_Array) + Net_Arr : Net_Array; + En : Net := No_Net) is Dat_W : constant Width := Get_Width (Dat); type Count_Type is record @@ -277,6 +278,7 @@ package body Netlists.Expands is Next_Off : Uns32; Prev_Net : Net; Step : Uns32; + S : Net; begin -- Initialize count. for I in Memidx_Arr'Range loop @@ -337,7 +339,12 @@ package body Netlists.Expands is V := Build_Extract (Ctxt, Mem, Off, Dat_W); end if; - V := Build_Mux2 (Ctxt, Net_Arr (Sel), V, Dat); + S := Net_Arr (Sel); + if En /= No_Net then + S := Build_Dyadic (Ctxt, Id_And, S, En); + end if; + + V := Build_Mux2 (Ctxt, S, V, Dat); Prev_Net := V; Next_Off := Off + Dat_W; @@ -364,7 +371,8 @@ package body Netlists.Expands is end loop; end Generate_Muxes; - procedure Expand_Dyn_Insert (Ctxt : Context_Acc; Inst : Instance) + procedure Expand_Dyn_Insert + (Ctxt : Context_Acc; Inst : Instance; En : Net) is Mem : constant Net := Get_Input_Net (Inst, 0); Dat : constant Net := Get_Input_Net (Inst, 1); @@ -413,6 +421,9 @@ package body Netlists.Expands is Disconnect (Get_Input (Inst, 0)); Disconnect (Get_Input (Inst, 1)); Disconnect (Get_Input (Inst, 2)); + if En /= No_Net then + Disconnect (Get_Input (Inst, 3)); + end if; Remove_Instance (Inst); end Expand_Dyn_Insert; @@ -456,7 +467,9 @@ package body Netlists.Expands is Expand_Dyn_Extract (Ctxt, Inst); when Id_Dyn_Insert => - Expand_Dyn_Insert (Ctxt, Inst); + Expand_Dyn_Insert (Ctxt, Inst, No_Net); + when Id_Dyn_Insert_En => + Expand_Dyn_Insert (Ctxt, Inst, Get_Input_Net (Inst, 3)); when Id_Rol => -- a rol b == shl (a, b) | shr (a, l - b) |