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| author | Tristan Gingold <tgingold@free.fr> | 2020-07-25 11:52:16 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-07-25 13:27:49 +0200 |
| commit | 6862e26f0a49d6871beb3454f1eb59ff33c35136 (patch) | |
| tree | 84260689b1b8f0bc8577c005a1eb4adb4acc78af /src | |
| parent | 9019f5175b84151d6f1d964f641266411078aa71 (diff) | |
| download | ghdl-6862e26f0a49d6871beb3454f1eb59ff33c35136.tar.gz ghdl-6862e26f0a49d6871beb3454f1eb59ff33c35136.tar.bz2 ghdl-6862e26f0a49d6871beb3454f1eb59ff33c35136.zip | |
trans-chap3: copy array subtype bounds from parent if derived
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/translate/trans-chap3.adb | 44 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_types.adb | 2 |
2 files changed, 33 insertions, 13 deletions
diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb index 4c7e5522b..fb6dc0ad3 100644 --- a/src/vhdl/translate/trans-chap3.adb +++ b/src/vhdl/translate/trans-chap3.adb @@ -690,28 +690,48 @@ package body Trans.Chap3 is when Iir_Kind_Array_Subtype_Definition => declare + Parent_Type : constant Iir := Get_Parent_Type (Def); + Parent_Tinfo : constant Type_Info_Acc := Get_Info (Parent_Type); + New_Indexes : constant Boolean := + not Get_Index_Constraint_Flag (Parent_Type); Indexes_List : constant Iir_Flist := Get_Index_Subtype_List (Def); El_Type : Iir; El_Tinfo : Type_Info_Acc; Targ : Mnode; + Rng : Mnode; Index : Iir; begin Targ := Layout_To_Bounds (Target); - -- Indexes - if Tinfo.B.Bounds_El /= O_Fnode_Null - or else Get_Nbr_Elements (Indexes_List) > 1 - then - Targ := Stabilize (Targ); + -- Indexes. + -- Set only if the array subtype has indexes constraints. + if Get_Index_Constraint_Flag (Def) then + if Tinfo.B.Bounds_El /= O_Fnode_Null + or else Get_Nbr_Elements (Indexes_List) > 1 + then + Targ := Stabilize (Targ); + end if; + for I in Flist_First .. Flist_Last (Indexes_List) loop + Index := Get_Index_Type (Indexes_List, I); + Open_Temp; + Rng := Bounds_To_Range (Targ, Def, I + 1); + if New_Indexes then + Chap7.Translate_Discrete_Range (Rng, Index); + else + Gen_Memcpy + (M2Addr (Rng), + M2Addr + (Bounds_To_Range + (Layout_To_Bounds + (Get_Composite_Type_Layout (Parent_Tinfo)), + Parent_Type, I + 1)), + New_Lit (New_Sizeof (Rng.M1.Vtype, + Ghdl_Index_Type))); + end if; + Close_Temp; + end loop; end if; - for I in Flist_First .. Flist_Last (Indexes_List) loop - Index := Get_Index_Type (Indexes_List, I); - Open_Temp; - Chap7.Translate_Discrete_Range - (Bounds_To_Range (Targ, Def, I + 1), Index); - Close_Temp; - end loop; -- Element. if Tinfo.B.Bounds_El /= O_Fnode_Null then diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 99c9646b5..969be9471 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -1689,7 +1689,7 @@ package body Vhdl.Sem_Types is Index_Staticness : Iir_Staticness; begin -- Check each index constraint against array type. - Set_Parent_Type (Def, Base_Type); + Set_Parent_Type (Def, Type_Mark); Sem_Array_Constraint_Indexes (Def, Type_Mark, Base_Type, Index_Staticness); |