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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-11 15:22:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-11 15:22:51 +0200 |
| commit | 5e4358bfee56ee068745923d167f466a4e950074 (patch) | |
| tree | c4b0d816762a9b6d3505f6c1e3ca8dce454f3d07 /src | |
| parent | 71ff56302baff001ea7d491a486143f0229a289b (diff) | |
| download | ghdl-5e4358bfee56ee068745923d167f466a4e950074.tar.gz ghdl-5e4358bfee56ee068745923d167f466a4e950074.tar.bz2 ghdl-5e4358bfee56ee068745923d167f466a4e950074.zip | |
synth: initialize variables with a static value.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-decls.adb | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index f0ccf71db..bf84ed41b 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -724,6 +724,7 @@ package body Synth.Decls is -- Slot : constant Object_Slot_Type := Get_Info (Decl).Slot; Init : Valtyp; Obj_Typ : Type_Acc; + Wid : Wire_Id; begin Synth_Declaration_Type (Syn_Inst, Decl); Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); @@ -747,10 +748,14 @@ package body Synth.Decls is else Create_Wire_Object (Syn_Inst, Wire_Variable, Decl); Create_Var_Wire (Syn_Inst, Decl, Init); + Wid := Get_Value (Syn_Inst, Decl).Val.W; if Is_Subprg then - Phi_Assign_Net - (Get_Build (Syn_Inst), - Get_Value (Syn_Inst, Decl).Val.W, Get_Net (Init), 0); + if Is_Static (Init.Val) then + Phi_Assign_Static (Wid, Get_Memtyp (Init)); + else + Phi_Assign_Net + (Get_Build (Syn_Inst), Wid, Get_Net (Init), 0); + end if; end if; end if; end if; |