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authorTristan Gingold <tgingold@free.fr>2019-09-21 08:52:24 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-21 08:52:24 +0200
commit3e83d4aa5076b1a8cf2ec2214de36c4f507078c9 (patch)
tree5fd7176bbe65f3a27b4ed9459e89867138ab2a4d /src
parent108c98263d15c50fd19fd39926dd6aa213d30b52 (diff)
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synth: add bit0/bit1 in instance.
Diffstat (limited to 'src')
-rw-r--r--src/synth/synth-context.adb13
-rw-r--r--src/synth/synth-context.ads6
-rw-r--r--src/synth/synth-insts.adb19
-rw-r--r--src/synth/synth-stmts.adb9
4 files changed, 33 insertions, 14 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index b6c5916b5..730f5b6aa 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -112,6 +112,9 @@ package body Synth.Context is
Cur_Module => M,
Bit0 => No_Net,
Bit1 => No_Net);
+ Builders.Set_Parent (Base.Builder, M);
+ Base.Bit0 := Build_Const_UB32 (Base.Builder, 0, 1);
+ Base.Bit1 := Build_Const_UB32 (Base.Builder, 1, 1);
Inst.Base := Base;
end Set_Instance_Module;
@@ -136,6 +139,16 @@ package body Synth.Context is
return Inst.Base.Builder;
end Get_Build;
+ function Get_Inst_Bit0 (Inst : Synth_Instance_Acc) return Net is
+ begin
+ return Inst.Base.Bit0;
+ end Get_Inst_Bit0;
+
+ function Get_Inst_Bit1 (Inst : Synth_Instance_Acc) return Net is
+ begin
+ return Inst.Base.Bit1;
+ end Get_Inst_Bit1;
+
function Create_Value_Instance (Inst : Synth_Instance_Acc)
return Value_Acc is
begin
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 296c89a78..708d42a73 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -61,6 +61,12 @@ package Synth.Context is
function Get_Instance_Module (Inst : Synth_Instance_Acc) return Module;
pragma Inline (Get_Instance_Module);
+ -- Each base instance creates bit0 and bit1, which are used for control
+ -- flow.
+ function Get_Inst_Bit0 (Inst : Synth_Instance_Acc) return Net;
+ function Get_Inst_Bit1 (Inst : Synth_Instance_Acc) return Net;
+ pragma Inline (Get_Inst_Bit0, Get_Inst_Bit1);
+
procedure Create_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 793717764..9996ccfbb 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -113,6 +113,7 @@ package body Synth.Insts is
Arch : Node;
Config : Node;
Syn_Inst : Synth_Instance_Acc;
+ M : Module;
end record;
function Hash (Params : Inst_Params) return Hash_Value_Type
@@ -162,6 +163,7 @@ package body Synth.Insts is
Nbr_Outputs : Port_Nbr;
Num : Uns32;
Cur_Module : Module;
+ Self_Inst : Instance;
begin
if Get_Kind (Params.Decl) = Iir_Kind_Component_Declaration then
pragma Assert (Params.Arch = Null_Node);
@@ -221,7 +223,6 @@ package body Synth.Insts is
Cur_Module := New_User_Module (Get_Top_Module (Root_Instance),
New_Sname_User (Get_Identifier (Decl)),
Id_User_None, Nbr_Inputs, Nbr_Outputs, 0);
- Set_Instance_Module (Syn_Inst, Cur_Module);
-- Add ports to module.
declare
@@ -248,10 +249,14 @@ package body Synth.Insts is
Set_Port_Desc (Cur_Module, Inports, Outports);
end;
+ Self_Inst := Create_Self_Instance (Cur_Module);
+ pragma Unreferenced (Self_Inst);
+
return Inst_Object'(Decl => Decl,
Arch => Arch,
Config => Params.Config,
- Syn_Inst => Syn_Inst);
+ Syn_Inst => Syn_Inst,
+ M => Cur_Module);
end Build;
package Insts_Interning is new Interning
@@ -371,7 +376,7 @@ package body Synth.Insts is
-- TODO: free sub_inst.
Inst := New_Instance (Get_Instance_Module (Syn_Inst),
- Get_Instance_Module (Inst_Obj.Syn_Inst),
+ Inst_Obj.M,
New_Sname_User (Get_Identifier (Stmt)));
Synth_Instantiate_Module
@@ -543,7 +548,7 @@ package body Synth.Insts is
-- TODO: free sub_inst.
Inst := New_Instance (Get_Instance_Module (Syn_Inst),
- Get_Instance_Module (Inst_Obj.Syn_Inst),
+ Inst_Obj.M,
New_Sname_User (Get_Identifier (Stmt)));
Synth_Instantiate_Module
@@ -764,7 +769,7 @@ package body Synth.Insts is
Entity : constant Node := Inst.Decl;
Arch : constant Node := Inst.Arch;
Syn_Inst : constant Synth_Instance_Acc := Inst.Syn_Inst;
- Self_Inst : Instance;
+ Self_Inst : constant Instance := Get_Self_Instance (Inst.M);
Inter : Node;
Nbr_Inputs : Port_Nbr;
Nbr_Outputs : Port_Nbr;
@@ -774,9 +779,7 @@ package body Synth.Insts is
return;
end if;
- Self_Inst := Create_Self_Instance (Get_Instance_Module (Syn_Inst));
- Builders.Set_Parent (Get_Build (Syn_Inst),
- Get_Instance_Module (Syn_Inst));
+ Set_Instance_Module (Syn_Inst, Inst.M);
-- Create wires for inputs and outputs.
Inter := Get_Port_Chain (Entity);
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index ddef62a74..d577ff17d 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -1318,8 +1318,7 @@ package body Synth.Stmts is
end if;
-- The subprogram has returned. Do not execute further statements.
- Phi_Assign (Build_Context, C.W_Ret,
- Build_Const_UB32 (Build_Context, 1, 1), 0);
+ Phi_Assign (Build_Context, C.W_Ret, Get_Inst_Bit1 (C.Inst), 0);
C.Nbr_Ret := C.Nbr_Ret + 1;
C.T_En := False;
end Synth_Return_Statement;
@@ -1521,13 +1520,11 @@ package body Synth.Stmts is
Set_Wire_Gate (C.W_Ret, Build_Signal (Build_Context,
New_Internal_Name (Build_Context),
1));
- Phi_Assign (Build_Context, C.W_Ret,
- Build_Const_UB32 (Build_Context, 0, 1), 0);
+ Phi_Assign (Build_Context, C.W_Ret, Get_Inst_Bit0 (Syn_Inst), 0);
Decls.Synth_Declarations (C.Inst, Get_Declaration_Chain (Bod), True);
- Synth_Sequential_Statements
- (C, Get_Sequential_Statement_Chain (Bod));
+ Synth_Sequential_Statements (C, Get_Sequential_Statement_Chain (Bod));
Pop_And_Merge_Phi (Build_Context, Bod);