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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-13 03:37:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-13 03:37:32 +0200 |
| commit | 359d7be5aae9ec4e487f6877df6c5368c16f6177 (patch) | |
| tree | 1ccab58e13ba7ce0ae28650e6dabff4f17bf40cd /src | |
| parent | 6010842641e0a478a957c68709b06be5f5b9ca3c (diff) | |
| download | ghdl-359d7be5aae9ec4e487f6877df6c5368c16f6177.tar.gz ghdl-359d7be5aae9ec4e487f6877df6c5368c16f6177.tar.bz2 ghdl-359d7be5aae9ec4e487f6877df6c5368c16f6177.zip | |
simul-vhdl_elab: fix crash on association with implicit signals
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 89e75e7c7..52f98817b 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -1020,7 +1020,10 @@ package body Simul.Vhdl_Elab is if Ns.Total = 0 and then Is_Out then Ns.Total := 1; end if; - if E.Collapsed_By /= No_Signal_Index then + if E.Collapsed_By /= No_Signal_Index + and then (Signals_Table.Table (E.Collapsed_By).Kind + in Mode_Signal_User) + then -- Add to the parent. declare C_Ns : Nbr_Sources_Type renames |