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| author | Tristan Gingold <tgingold@free.fr> | 2016-03-07 07:02:17 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-03-10 08:01:09 +0100 |
| commit | 2acd82b0fb925dee18536b03f592459492e98703 (patch) | |
| tree | 0de9ce8cd7443c1a0b795e0b48810d8bdda57051 /src | |
| parent | 61b5b41b0e9a3c9449f0b177517ac495e2adc5f3 (diff) | |
| download | ghdl-2acd82b0fb925dee18536b03f592459492e98703.tar.gz ghdl-2acd82b0fb925dee18536b03f592459492e98703.tar.bz2 ghdl-2acd82b0fb925dee18536b03f592459492e98703.zip | |
elaboration: use std_time to represent time in signal table.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/elaboration.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/simulate/elaboration.ads | 3 | ||||
| -rw-r--r-- | src/vhdl/simulate/simulation-main.adb | 9 |
3 files changed, 9 insertions, 9 deletions
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 33868a804..ed9a02fe6 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -218,7 +218,7 @@ package body Elaboration is Sig => Sig, Val => Init, Instance => Instance, - Time => T, + Time => Std_Time (T), Prefix => Prefix)); when Implicit_Quiet => Signals_Table.Append ((Kind => Implicit_Quiet, @@ -226,7 +226,7 @@ package body Elaboration is Sig => Sig, Val => Init, Instance => Instance, - Time => T, + Time => Std_Time (T), Prefix => Prefix)); when Implicit_Transaction => Signals_Table.Append ((Kind => Implicit_Transaction, @@ -299,7 +299,7 @@ package body Elaboration is Sig => Sig, Val => Init, Instance => Instance, - Time => T, + Time => Std_Time (T), Prefix => Prefix)); end Elaborate_Delayed_Signal; diff --git a/src/vhdl/simulate/elaboration.ads b/src/vhdl/simulate/elaboration.ads index 91cb04f7b..dc7965413 100644 --- a/src/vhdl/simulate/elaboration.ads +++ b/src/vhdl/simulate/elaboration.ads @@ -183,6 +183,7 @@ package Elaboration is Table_Initial => 32); -- Signals. + -- FIXME: use Mode_Signal_Type instead ? type Signal_Type_Kind is (User_Signal, Implicit_Quiet, Implicit_Stable, Implicit_Delayed, @@ -199,7 +200,7 @@ package Elaboration is null; when Implicit_Quiet | Implicit_Stable | Implicit_Delayed | Implicit_Transaction => - Time : Grt.Types.Ghdl_I64; + Time : Grt.Types.Std_Time; Prefix : Iir_Value_Literal_Acc; when Guard_Signal => null; diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb index d4b26320f..cd93165da 100644 --- a/src/vhdl/simulate/simulation-main.adb +++ b/src/vhdl/simulate/simulation-main.adb @@ -849,7 +849,7 @@ package body Simulation.Main is procedure Create_Implicit_Signal (Sig : Iir_Value_Literal_Acc; Val : Iir_Value_Literal_Acc; - Time : Ghdl_I64; + Time : Std_Time; Prefix : Iir_Value_Literal_Acc; Kind : Signal_Type_Kind) is @@ -874,10 +874,10 @@ package body Simulation.Main is case Kind is when Implicit_Stable => Sig.Sig := Grt.Signals.Ghdl_Create_Stable_Signal - (To_Ghdl_Value_Ptr (Val.B1'Address), Std_Time (Time)); + (To_Ghdl_Value_Ptr (Val.B1'Address), Time); when Implicit_Quiet => Sig.Sig := Grt.Signals.Ghdl_Create_Quiet_Signal - (To_Ghdl_Value_Ptr (Val.B1'Address), Std_Time (Time)); + (To_Ghdl_Value_Ptr (Val.B1'Address), Time); when Implicit_Transaction => Sig.Sig := Grt.Signals.Ghdl_Create_Transaction_Signal (To_Ghdl_Value_Ptr (Val.B1'Address)); @@ -1076,8 +1076,7 @@ package body Simulation.Main is Create_Implicit_Signal (E.Sig, E.Val, E.Time, E.Prefix, E.Kind); when Implicit_Delayed => - Create_Delayed_Signal (E.Sig, E.Val, - E.Prefix, Std_Time (E.Time)); + Create_Delayed_Signal (E.Sig, E.Val, E.Prefix, E.Time); when User_Signal => Create_User_Signal (E.Instance, E.Decl, E.Sig, E.Val); end case; |