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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-21 20:41:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-21 20:41:35 +0200 |
| commit | 200daa4a69cbbd29708a4d58db65ae59d2bf3e1e (patch) | |
| tree | d92902144a0ca46bb680e0d959166c9be00daaa5 /src | |
| parent | c9c04ce167a18eb0bf54dbef71244c892e8c04ec (diff) | |
| download | ghdl-200daa4a69cbbd29708a4d58db65ae59d2bf3e1e.tar.gz ghdl-200daa4a69cbbd29708a4d58db65ae59d2bf3e1e.tar.bz2 ghdl-200daa4a69cbbd29708a4d58db65ae59d2bf3e1e.zip | |
synth-vhdl_oper.adb: handle resize uns/uns. For #1731
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 26a886edf..2c3252a83 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1960,6 +1960,18 @@ package body Synth.Vhdl_Oper is (Synth_Uresize (Ctxt, L, W, Expr), Create_Vec_Type_By_Length (W, Logic_Type)); end; + when Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Uns => + declare + B : Bound_Type; + W : Width; + begin + B := Get_Array_Bound (R.Typ, 1); + W := B.Len; + return Create_Value_Net + (Build2_Uresize (Ctxt, Get_Net (Ctxt, L), + W, Get_Location (Expr)), + Create_Vec_Type_By_Length (W, Logic_Type)); + end; when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn |