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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-03 07:53:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-04 19:04:06 +0200 |
| commit | 012cd7bb501aea20b41fc63516e67256dc62fd5c (patch) | |
| tree | 1ccc913eb47f1620564cdc8cb9ea9b9e567a3926 /src | |
| parent | 02a92af133fe9e1c9beeedbbe6f8e664fbd4e7cc (diff) | |
| download | ghdl-012cd7bb501aea20b41fc63516e67256dc62fd5c.tar.gz ghdl-012cd7bb501aea20b41fc63516e67256dc62fd5c.tar.bz2 ghdl-012cd7bb501aea20b41fc63516e67256dc62fd5c.zip | |
synth-environment: minor change to ease debugging.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-environment.adb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index ff295dba9..6ae560a2f 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -51,7 +51,9 @@ package body Synth.Environment is end Get_Wire_Mark; function Alloc_Wire (Kind : Wire_Kind; Obj : Source.Syn_Src) - return Wire_Id is + return Wire_Id + is + Res : Wire_Id; begin Wire_Id_Table.Append ((Kind => Kind, Mark_Flag => False, @@ -60,7 +62,8 @@ package body Synth.Environment is Cur_Assign => No_Seq_Assign, Final_Assign => No_Conc_Assign, Nbr_Final_Assign => 0)); - return Wire_Id_Table.Last; + Res := Wire_Id_Table.Last; + return Res; end Alloc_Wire; procedure Free_Wire (Wid : Wire_Id) |