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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-09 19:50:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-09 19:50:09 +0200 |
| commit | 8d7b1e86851c45778d316fc174eef15a1a34af49 (patch) | |
| tree | 15e47769460942b2506652a0d52c56e81a71dcdd /src/vhdl/vhdl-sem_lib.adb | |
| parent | f24e92d2cefff069acf6e5cc6954432f09889dae (diff) | |
| download | ghdl-8d7b1e86851c45778d316fc174eef15a1a34af49.tar.gz ghdl-8d7b1e86851c45778d316fc174eef15a1a34af49.tar.bz2 ghdl-8d7b1e86851c45778d316fc174eef15a1a34af49.zip | |
vhdl-sem_lib: Load_Parse_Design_Unit: ignore checksum if
Diffstat (limited to 'src/vhdl/vhdl-sem_lib.adb')
| -rw-r--r-- | src/vhdl/vhdl-sem_lib.adb | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb index 4bd8363d2..dab415789 100644 --- a/src/vhdl/vhdl-sem_lib.adb +++ b/src/vhdl/vhdl-sem_lib.adb @@ -182,6 +182,7 @@ package body Vhdl.Sem_Lib is Line, Off: Natural; Pos: Source_Ptr; Res: Iir; + Checksum : File_Checksum_Id; begin -- The unit must not be loaded. pragma Assert (Get_Date_State (Design_Unit) = Date_Disk); @@ -198,9 +199,11 @@ package body Vhdl.Sem_Lib is end if; Set_Design_File_Source (Design_File, Fe); - -- Check if the file has changed. - if not Files_Map.Is_Eq - (Files_Map.Get_File_Checksum (Fe), Get_File_Checksum (Design_File)) + -- Check if the file has changed (but only if it has a checksum). + Checksum := Get_File_Checksum (Design_File); + if Checksum /= No_File_Checksum_Id + and then + not Files_Map.Is_Eq (Files_Map.Get_File_Checksum (Fe), Checksum) then Error_Msg_Sem (+Loc, "file %i has changed and must be reanalysed", +Get_Design_File_Filename (Design_File)); |