vhdl: add a warning to detect use before elaboration

1 files changed, 7 insertions, 0 deletions

diff --git a/src/vhdl/vhdl-sem_expr.ads b/src/vhdl/vhdl-sem_expr.ads
index 1519d9252..b247d2d7e 100644
--- a/src/vhdl/vhdl-sem_expr.ads
+++ b/src/vhdl/vhdl-sem_expr.ads
@@ -24,8 +24,15 @@ package Vhdl.Sem_Expr is
    --  Set type to nodes,
    --  Resolve overloading
 
+   --  If set, use of deferred constants is allowed.
+   --  Set during analysis of default value of subprogram parameters.
    Deferred_Constant_Allowed : Boolean := False;
 
+   --  If set, use of unelaborated constructs is allowed.
+   --  This is set while analyzing subprograms body (and default parameters
+   --  values), as a subprogram may be called way after elaboration.
+   Unelaborated_Use_Allowed : Boolean := False;
+
    --  Analyze an expression (other than a range) with a possible overloading.
    --  Sem_expression_ov (and therefore sem_expression) must be called *once*
    --  for each expression node with A_TYPE1 not null and at most *once* with