vhdl: replace base_type with parent_type in nodes

Only for subtype definition and remove base_type in type definitions.
Allows to better track the addition of contraints.

1 files changed, 0 insertions, 1 deletions

diff --git a/src/vhdl/vhdl-nodes.adb.in b/src/vhdl/vhdl-nodes.adb.in
index 913f54f7e..5c77f9fef 100644
--- a/src/vhdl/vhdl-nodes.adb.in
+++ b/src/vhdl/vhdl-nodes.adb.in
@@ -842,7 +842,6 @@ package body Vhdl.Nodes is
    begin
       Res := Create_Node (Format_Short);
       Set_Nkind (Res, Iir_Kind'Pos (Iir_Kind_Error));
-      Set_Base_Type (Res, Res);
       return Res;
    end Create_Iir_Error;