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authorTristan Gingold <tgingold@free.fr>2019-07-14 07:04:56 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-14 08:31:58 +0200
commit1b78b16bd6ffde3cf5ab83f5e3cb65d9dfc09b85 (patch)
treedb2d7a81c84945a532acc09481df9451b885fa53 /src/vhdl/vhdl-configuration.ads
parente837a3899bb7d2bd8dc4d99ae0cb10ae0d4a1a75 (diff)
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ghdlsynth: check top entity can be a top entity.
Diffstat (limited to 'src/vhdl/vhdl-configuration.ads')
-rw-r--r--src/vhdl/vhdl-configuration.ads3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-configuration.ads b/src/vhdl/vhdl-configuration.ads
index c6a5105cd..8cadad8fc 100644
--- a/src/vhdl/vhdl-configuration.ads
+++ b/src/vhdl/vhdl-configuration.ads
@@ -51,7 +51,8 @@ package Vhdl.Configuration is
-- ENTITY has no generics or all generics have a default expression
-- ENTITY has no ports or all ports type are constrained.
-- If not, emit a elab error message.
- procedure Check_Entity_Declaration_Top (Entity : Iir_Entity_Declaration);
+ procedure Check_Entity_Declaration_Top
+ (Entity : Iir_Entity_Declaration; Enable_Override : Boolean);
-- Use heuritics to find the top entity in FROM (either a library or
-- a design file): mark all instantiated units and return the unmarked